Unit Time Delay Research Articles

A method of synthesis and decomposition of autonomous linear sequential circuits

We describe one of the practical methods to synthesize and decompose the autonomous linear sequential circuit (ALSC). The method for decomposition includes two steps. First, we discuss the behavior of the linear sequential circuit (LSC) with a feedback which has a unit time delay. Next, we derive the relation between the number of cycles (which correspond to a periodic output sequence) and that of states. In a forward I-S permutation LSC the number p of cycles is given as 1 ⩽ p ⩽ n ( n + 1)/2, where n is the number of states. While, the largest length of a cycle on a I-S permutation LSC may be n 2 . The necessary and sufficient condition that the state transition diagram of a forward I-S permutation LSC A consists of only cycles is that A is a reverse I-S permutation LSC. Moreover, the decomposition theorem of the resultant LSC is obtained from Hartmanis' theorem.

Iterative Switching Networks Composed of Combinational Cells

The networks considered in this paper consist of n identical combinational logic cells connected in cascade through bi-directional discrete information channels. All switching is done synchronously with unit time delay through each cell. Three classes of networks are formed according to whether or not information flow in one direction along the cascade is dependent upon that in the other. Steady-state behavioral relationships between the three classes are discussed, and the class having mutually dependent information flow is shown to be the only one which can exhibit steady-state memory properties. The main object of the paper is to derive several theorems concerning these memory properties. The last section interprets some previous results of Hennie as a start on the transients and cycling problems.