Uniform Traffic Pattern Research Articles

RPNoC: A Ring-Based Packet-Switched Optical Network-on-Chip

Optical network-on-chip (ONoC) is a promising solution for its high bandwidth and low energy consumption. However, optical circuit switching requires an electrical control network, which leads to network congestion, low network utilization, high latency, and an overhead in energy consumption. In this letter, we propose an architecture called RPNoC based on ring topology using packet switching. A wavelength assignment method and a deadlock-free deterministic routing algorithm are jointly designed, which significantly reduce the maximum number of hops using much fewer optical devices compared with other packet-switched ONoCs. The simulation is carried out for 64-node RPNoC under uniform and realistic traffic pattern. The evaluation results show that it yields higher throughput, lower latency, and lower energy consumption than mesh and ring networks.

Uniform Traffic Patterns using Virtual Cut-Through Flow Control on VMMN

Abstract The previous study of static network performance of a Vertical Midimew connected Mesh Network (VMMN) was shown to be good. However, its dynamic communication performance has not been evaluated yet, we have proposed a deadlock free dimension order routing algorithm using 4 virtual channels. In this paper, The TOPAZ simulator is used to evaluate the dynamic communication performance of a VMMN with virtual cut-through flow control under uniform traffic pattern. We found that the VMMN dynamic communication performance is better than that of the hierarchical TESH network and its counter rival MMN.

On Uniform Traffic Pattern of Symmetric Midimew Connected Mesh Network

A Symmetric Midimew Mesh connected network (SMMN) is a hierarchical interconnection networks (HIN) that capable to interconnect vast number of nodes that could reach up to millions of nodes in the network. SMMN has multiple basic modules of 2D-mesh networks that are recursively interconnected by Midimew network to create higher-level networks. In this paper, we explain the architectural details of SMMN,we also present the a deadlock-free routing algorithm for SMMN using four virtual channels and evaluate the performance of dynamic communication of SMMN network using proposed routing algorithm under uniform traffic pattern .We also evaluate the performance of dynamic communication of TESH network using topaz simulator. It is shown that the SMMN network has high throughput and low latency, which yield higher performance of dynamic communication compare to other Hierarchical networks.

New Path-Setup Method for Optical Network-on-Chip

With high bandwidth, low interference, and low power consumption, optical network-on-chip (ONoC) has emerged as a highly efficient interconnection for the future generation of multicore system on chips. In this paper, we propose a new path-setup method for ONoC to mitigate contentions, such as packets, by recycling the setup packet halfway to the destination. A new, strictly non-blocking optical router is designed to support the new method. The simulation results show the new path-setup method increases the throughput by 52.03%, 41.94%, and 36.47% under uniform, hotspot-I, and hotspot-II traffic patterns, respectively. The end-to-end delay performance is also improved.

Performance of Dynamic Pump-Wavelength Selection for Optical Packet Switch With Chained Parametric Wavelength Conversion

This paper proposes a scheme for pump-wavelength selection in an optical packet switch (OPS) with parametric wavelength converters (PWCs). In this scheme, pump wavelengths can be dynamically changed in all time slots, and more than one PWC is allowed to convert a wavelength in a chained manner. The objective of this scheme is to minimize the packet loss rates of the OPS. This scheme is called dynamic pump-wavelength selection with chained parametric wavelength conversion (DPS-C). DPS-C selects the pump wavelength for each PWC so as to maximize the number of successful requests, which refer to packets that wish to be forwarded to their requested output fibers. A PWC, which has the advantage of multiple wavelength conversion, uses a pump wavelength that can be flexibly chosen to define which wavelengths can be converted from/to. The set of original and converted wavelengths, where the pump wavelength is set in the middle of the two wavelengths, is called the conversion pair. Each PWC supports several conversion pairs. The OPS allows each wavelength to be converted using combinations of available conversion pairs, which are not used by any requests, from more than one PWC. A simulation shows that DPS-C outperforms the conventional scheme in terms of packet loss rates in both uniform and nonuniform traffic patterns.

Performance modelling of adaptive routing communication networks in multi-cluster systems under bit-reversal traffic

Several analytical models of interconnection networks of multi-cluster systems under uniform traffic pattern have been proposed in the literature. However, there has been hardly any work reported yet that deals with other important non-uniform traffic patterns found in many parallel applications. In this paper we propose a new analytical model of adaptive routing in fat-tree-based interconnection networks in the presence of traffic pattern generated by bit-reversal permutation, which is an important communication operation in parallel applications such as FFT computations. The model is validated through comprehensive simulation, through which the proposed model exhibited a good degree of accuracy for various system organisations and under different working conditions.

Complex network-enabled robust wireless network-on-chip architectures

The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern multicore chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional multihop metal/dielectric-based interconnects. Three-dimensional integration, on-chip photonics, RF, and wireless links have been proposed as radical low-power and low-latency alternatives to the conventional planar wire-based designs. Wireless NoCs with Carbon NanoTube (CNT) antennas are shown to outperform traditional wire-based NoCs significantly in achievable data rate and energy dissipation. However, such emerging and transformative technologies will be prone to high levels of failures due to various issues related to manufacturing challenges and integration. On the other hand, several naturally occurring complex networks such as colonies of microbes and the World Wide Web are known to be inherently robust against high rates of failures and harsh environments. This article advocates adoption of such complex network-based architectures to minimize the effect of wireless link failures on the performance of the NoC. Through cycle-accurate simulations it is shown that the wireless NoC architectures inspired by natural complex networks perform better than their conventional wired counterparts even in the presence of high degrees of link failures. We demonstrate the robustness of the proposed wireless NoC architecture by incorporating both uniform and application-specific traffic patterns.

Analytical performance modeling of shuffle–exchange inspired mesh-based Network-on-Chips

This paper proposes and evaluates a shuffle–exchange as an efficient alternative to the popular mesh topology for Network-on-Chips (NoCs). Although the proposed topology imposes the cost equal to that of the mesh topology, the proposed topology (1) provides lower diameter for NoC, (2) offers better performance under uniform, hotspot, and matrix-transpose traffic patterns and (3) consumes lower energy for packet delivery. To speed up the evaluation process of the proposed topology, an analytical performance model is proposed in the paper to predict the performance of NoCs. The model uses a network of M/G/1 queues to consider channels of the NoC. In this way, the model accurately estimates the average message latency which is a widely used representative for the network performance. Results obtained from the analytical model are in good agreement with those of simulations for a wide range of working conditions (e.g. various network sizes, different message lengths, and different traffic patterns). The proposed analytical model provides a minimum of 400% speed-up in the evaluation process of the proposed topology.

Cluster Based Networks-on-Chip

Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, the authors present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5×6 crossbar is used for the proposed architecture which requires one more 5×1 multiplexer without increasing the critical path delay of the router as compared to the 5×5 crossbar. The proposed router has been simulated for uniform, transpose and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead.

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip

Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer ultrahigh communication bandwidth and low latency to multiprocessor systems-on-chip (MPSoCs). In addition to ONoC architectures, 3-D integrated technologies offer an opportunity to continue performance improvements with higher integration densities. In this paper, we present a 3-D mesh-based ONoC for MPSoCs, and new low-cost nonblocking 4 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 4, 5 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\,\times\,$</tex></formula> 5, 6 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 6, and 7 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 7 optical routers for dimension-order routing in the 3-D mesh-based ONoC. Besides, we propose an optimized floorplan for the 3-D mesh-based ONoC. The floorplan follows the regular 3-D mesh topology but implements all optical routers in a single optical layer. The floorplan is optimized to minimize the number of extra waveguide crossings caused when merging the 3-D ONoC to one optical layer. Based on a set of real applications and uniform traffic pattern, we develop a SystemC-based cycle-accurate NoC simulator and compare the 3-D mesh-based ONoC with the matched 2-D mesh-based ONoC and 2-D electronic NoC for performance and energy efficiency. Additionally, we quantitatively analyze thermal effects on the 3-D 8 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\,\times\,$</tex></formula> 8 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 2 mesh-based ONoC.

Flexible router architecture for network-on-chip

The growing complexity of systems-on-chip (SoCs) pushes researchers to propose replacing the bus architecture by Networks-on-Chip (NoCs). The key advantages of NoCs are efficient exploitation of performance and scalability. Nowadays NoCs are a well established research topic and several implementations have been proposed. Some techniques are proposed to improve NoC performance in terms of latency and throughput while others are proposed to improve area utilization and power consumption. An important research in NoC design is the tradeoff between area/power and performance. In order to improve performance some techniques tend to increase the number of buffers. However this method increases area and power consumption. This paper introduces new router architecture, called the Flexible Router, which improves the performance of the overall network using the same amount of available buffers but in more efficient way. Therefore there is no need to increase the size of buffers or to use extra virtual channels (VCs) which cause high power consumption, area overheads, and complex logic. The Flexible Router provides a way to handle the requests to a busy buffer by other buffers in the router. It is observed that the Flexible router can achieve better performance in terms of increasing the saturation rate for Hotspot, Uniform, and Nearest-Neighbor traffic patterns, especially Hotspot with an 11.4% increase. Discussion about area overhead compared to the Base router and analysis of arriving out of order packets (side-effect) are also provided.

A single-cycle output buffered router with layered switching for Networks-on-Chips

We present a single-cycle output buffered router based on layered switching for networks on chips (NoCs). Different from state-of-the-art NoC routers, the router has three important characteristics: (1) It employs layered switching, which implements wormhole on top of virtual cut-through (VCT) switching; (2) In contrast to input buffered architectures, it adopts an output buffered architecture; (3) It is single cycle, meaning that the router pipeline takes only one cycle for all flits. Experimental results show that the router achieves up to 80% of ideal network throughput under uniform random traffic pattern. Compared with wormhole switching, layered switching achieves up to 36.9% latency reduction for 12-flit packets under uniform random traffic with an injection rate of 0.5 flit/cycle/node. Under 65nm technology synthesized results show that its critical path has only 20 logic gates, and it reduces 11% area compared to the input virtual-channel router with the same buffer capacity.

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. However, in existing optical NoCs, communication locality is poorly supported, and the importance of floorplanning is overlooked. These significantly limit the power efficiency and performance of optical NoCs. In this work, we address these issues and propose a torus-based hierarchical hybrid optical-electronic NoC, called THOE. THOE takes advantage of both electrical and optical routers and interconnects in a hierarchical manner. It employs several new techniques including floorplan optimization, an adaptive power control mechanism, low-latency control protocols, and hybrid optical-electrical routers with a low-power optical switching fabric. Both of the unfolded and folded torus topologies are explored for THOE. Based on a set of real MPSoC applications, we compared THOE with a typical torus-based optical NoC as well as a torus-based electronic NoC in 45nm on a 256-core MPSoC, using a SystemC-based cycle-accurate NoC simulator. Compared with the matched electronic torus-based NoC, THOE achieves 2.46X performance and 1.51X network switching capacity utilization, with 84% less energy consumption. Compared with the optical torus-based NoC, THOE achieves 4.71X performance and 3.05X network switching capacity utilization, while reducing 99% of energy consumption. Besides real MPSoC applications, a uniform traffic pattern is also used to show the average packet delay and network throughput of THOE. Regarding hardware cost, THOE reduces 75% of laser sources and half of optical receivers compared with the optical torus-based NoC.

On Nonuniform Traffic Pattern of Modified Hierarchical 3D-Torus Network

A Modified Hierarchical 3D-Torus (MH3DT) network is a 3D-torus network consisting of multiple basic modules, in which each basic module itself is a 3D-torus network. Inter-node communication performance has been evaluated using dimension-order routing and 2 virtual channels (VCs) under uniform traffic patterns but not under non-uniform traffic patterns. In this paper, we evaluate the inter-node communication performance of MH3DT under five non-uniform traffic patterns and compare it with other networks. We found that under non-uniform traffic patterns, the MH3DT yields high throughput and low latency, providing better inter-node communication performance compared to H3DT, TESH, mesh, and torus networks. Also, we found that non-uniform traffic patterns have higher throughput than uniform traffic in the MH3DT network.

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip

Electrical network-on-chip (NoC) faces critical challenges in meeting the high performance and low power consumption requirements for future multicore processors interconnection. Recent tremendous advances in CMOS compatible optical components give the potential for photonics to deliver an efficient NoC performance at an acceptable energy cost. However, the lack of in flight processing and buffering of optical data made the realization of a fully optical NoC complicated. A hybrid architecture which uses optical high bandwidth transfer and an electrical control network can take advantage of both interconnection methods to offer an efficient performance-per-watt infrastructure to connect multicore processors and system-on-chip (SoC). In this paper, we propose a predictive switching and a reservation based path setup techniques to reduce the path setup latency of such hybrid photonic network-on-chip (HPNoC). By using these techniques, it is possible to reduce the latency for end-to-end communication in a HPNoC improving its overall performance. In the simulation, we use a cycle accurate simulator under uniform, neighbor, and bitreversal traffic patterns for a 64-node torus topology. The results show that the proposed techniques considerably improve the overall latency of HPNoC.

Dynamic Channel Assignment for Large-Scale Cellular Networks Using Noisy Chaotic Neural Network

This paper presents a novel dynamic channel assignment (DCA) technique for large-scale cellular networks (LCNs) using noisy chaotic neural network. In this technique, an LCN is first decomposed into many subnets, which are designated as decomposed cellular subnets (DCSs). The DCA process is independently performed in every subnet to alleviate the signaling overheads and to apportion the DCA computational load among the subnets. Then a novel energy function is formulated to avoid causing mutual interference among neighboring subnets based on the real-time interference channel table. In each subnet, the proposed energy function also satisfies three interference constraints among cells and the number of required channels of each cell, and simultaneously minimizes the total number of assigned channels to improve spectrum utilization. A typical 441-cell LCN with 70 available channels, which can be decomposed into nine 49-cell DCSs, is examined to demonstrate the validity of the proposed technique by blocking probability, including uniform and hot spot traffic patterns.

Impact of scheduling algorithms on performance of crosspoint-queued switch

The performance analysis of the 32 × 32 crosspoint-queued switch is presented in this paper. Switches with small buffers in crosspoints have been evaluated in the late 1980s but mostly for uniform traffic. However, due to technological limitations of that time, it was impractical to implement large buffers together with switching fabric. The crosspoint-queued switch architecture has been recently brought back into focus since modern technology enables an easy implementation of large buffers in crosspoints. An advantage of this solution is the absence of control communication between linecards and schedulers. In this paper, the performances of four algorithms (longest queue first, round robin, exhaustive round robin, and frame-based round robin matching) are analyzed and compared. The results obtained for the crosspoint-queued switch are compared with the output queued switch. Throughput, average cell latency and instantaneous packet delay variance are evaluated under uniform and nonuniform traffic patterns. The results will show that the longest queue first algorithm has the highest throughput in many simulated cases but the highest average cell latency and delay variance among observed algorithms. It will also be shown that the choice of the scheduling algorithm does not play a role in the switch performance if the buffers are long enough. This will prove that some form of round-robin-based algorithms become a better choice for implementation due to their simplicity, small hardware requirements, and avoidance of the starvation problem, which is a major drawback of the longest queue first algorithm.

Modeling the effects of hot-spot traffic load on the performance of wormhole-switched hypermeshes

Hypermesh is a promising network topology and is suitable for a range of network-based computing systems. Although there are few models reported for hypermeshes with uniform traffic pattern, no analytical model has been reported to deal with hot-spot traffic. Since many parallel applications exhibit non-uniform traffic patterns such as hot-spots, uniform traffic assumption is not always justifiable in practice. In this study, we propose a new analytical model to predict the mean message latency in wormhole-switched hypermeshes in the presence of hot-spot traffic. The proposed model can also calculate the mean latency under uniform traffic load when the hot-spot ratio is set to zero. Simulation results show the validity and the reasonable accuracy of the model even under heavy traffic loads and near saturation region.

Using Consumer-Based Kiosk Technology to Improve and Standardize Medication Reconciliation in a Specialty Care Setting

Discrepancies in medication documentation most often occur at handoffs or transition points in care. A process improvement team at the Portland Department of Veterans Affairs developed a standardized medication reconciliation process for the Portland chemotherapy administration unit, a physically self-contained clinic with a standard intake process and a uniform patient traffic pattern. The team developed the automated patient history intake device (APHID), a reconciliation software program accessed by the patient using a computer terminal kiosk in the clinic lobby. The program simultaneously checks in patients for an appointment and gathers a medication-adherence history by retrieving medication lists from all Veterans Affairs facilities and pairing each medication with a pill picture. Installation of the APHID kiosk included an initial two-week roll-in period beginning in February 2008. During the roll-in period, 91 (82.0%) of 111 patients completed check-in and performed medication reconciliation using the kiosk. Medication lists gathered at the kiosk were compared with existing health record documentation and clinician interviews. For each patient encounter, the process demonstrated an average of 4.59 discrepancies and an average of 1.61 clinically significant or potentially lethal discrepancies. The new process saved approximately 0.24 full-time equivalents of nursing time in the chemotherapy clinic-a nearly 50% reduction in nursing time dedicated to reconciliation activities without an apparent loss in data accuracy. A patient-centered reconciliation model using consumer-based kiosk technology helped providers efficiently retrieve a comprehensive list of medications across a geographically diverse area and improve patient medication recall using visual cues including medication pictures.

TTN: A High Performance Hierarchical Interconnection Network for Massively Parallel Computers

Interconnection networks play a crucial role in the performance of massively parallel computers. Hierarchical interconnection networks provide high performance at low cost by exploring the locality that exists in the communication patterns of massively parallel computers. A Tori connected Torus Network (TTN) is a 2D-torus network of multiple basic modules, in which the basic modules are 2D-torus networks that are hierarchically interconnected for higher-level networks. This paper addresses the architectural details of the TTN and explores aspects such as node degree, network diameter, cost, average distance, arc connectivity, bisection width, and wiring complexity. We also present a deadlock-free routing algorithm for the TTN using four virtual channels and evaluate the network's dynamic communication performance using the proposed routing algorithm under uniform and various non-uniform traffic patterns. We evaluate the dynamic communication performance of TTN, TESH, MH3DT, mesh, and torus networks by computer simulation. It is shown that the TTN possesses several attractive features, including constant node degree, small diameter, low cost, small average distance, moderate (neither too low, nor too high) bisection width, and high throughput and very low zero load latency, which provide better dynamic communication performance than that of other conventional and hierarchical networks.