Uniform Traffic Pattern Research Articles

An efficient adaptive routing algorithm for the Co-optimization of fault tolerance and congestion awareness based on 3D NoC

In this paper, we propose an adaptive, fault-tolerant, and congestion-aware (AFTC) routing algorithm. It improves the overall network performance of three-dimensional Network-on-Chip (3D NoC) in terms of deadlock-free, adaptability, fault tolerance, and balanced traffic. Firstly, the algorithm proposed 12 turn models to avoid deadlock problems. Then, the adaptability of the algorithm is improved by using the three-dimensional diagonal region division method. At the same time, the AFTC can reduce the number of turn-around steps during fault tolerance. Finally, the AFTC can balance traffic by setting different congestion thresholds. Compared with Vertical-Mesh-Conscious-Dynamic (VMCD) algorithm in terms of average packet delay and throughput, the AFTC algorithm can improve the throughput by an average of 27.29 % and 18.62 % while reducing the average delay time in different fault rates under uniform traffic and hotspot traffic patterns, respectively.

Making path selection faster: a routing algorithm for ONoC.

Optical network-on-chip (ONoC) is an effective communication architecture to realize high performance and energy efficiency. Diverse routing algorithms are proposed to avoid the congestion, tolerate the faults, and reduce the insertion loss or energy consumption. However, existing algorithms did not consider the characteristic optical circuit-switching of ONoC, which aggravates the network congestion and degrades the associated performance severely. In this paper, by exploiting congestion prediction technique, we propose a new routing algorithm for ONoC, named loophole-routing, to improve the success rate of path-setup and decrease the latency. We use the congestion prediction technique to analyze the latency and predict the port condition caused by the network congestion. Theoretical analysis and experimental results of different synthetic traffic patterns show that the loophole-routing improves network latency over XY routing and OE-turn routing by 15.56%, 25.71%, 18.92%, 66.67% and 42.86% under uniform, hotspot1, hotspot2, transpose2 and transpose3 traffic patterns while improving the saturation throughput by 31.43%, 34.33%, 35.29%, 67.86% and 99.5% under uniform, hotspot1, hotspot2, transpose2 and transpose3 traffic patterns on average than XY routing. In addition, our proposed loophole-routing has the benefits of high path diversity and adaptive degree and low computing complexity and overhead and the potential to make fault-tolerant path selection.

Energy-efficient and sustainable communication in optical networks on chip

Communication among nodes plays an important role in any system's throughput. In some architecture, communication plays a bottleneck which degrades the computation power. However, making a high-performance computational system along with the energy-efficient system is incompatible in many cases. In this paper, we present a routing methodology in an optical networks on chip (O-NoC). The proposed methodology includes architectural design as well as algorithms working on that architecture. These algorithms are used to communicate among nodes, which eliminates path reservation criteria and provides guaranteed communication. Under some criteria, our methodology achieved excellent results in reducing design space complexity. Furthermore, we evaluated our results on synthetic traffic patterns which include random uniform and hotspot traffic patterns. The proposed methodology achieves better results in case of reduction in hop count between nodes, 100 % link utilization which eliminates ideal node and reduces algorithm running time that makes architecture more energy efficient. These achieved results may enhance computation power and communication power at the same time in O-NoC.

Flow control and scheduling mechanism to improve network performance in wireless NoC

Today's, a promising solution, namely wireless network-on-chip (WiNoC) is utilized in multi-core systems to overcome the constraints of conventional on-chip networks. In WiNoC architectures, wireless routers (WRs) provide high capacity wireless links to reduce the latency of multi-hop communications. However, the buffer size of the WR antenna is limited, and under heavy traffic loads, it's filled and congestion occurs. On the other hand, network performance is degraded severely in the presence of head-of-line (HOL) blocking. Therefore, flow control and scheduling mechanisms are vital for improving the performance of WiNoCs. In this study, a flow control scheme based on an active queue management algorithm, and a priority-based scheduling strategy are suggested. The proposed mechanisms are evaluated under uniform and Bit-complement traffic patterns with different packet injection rate. The simulation results show that the proposed schemes have a significant impact on performance parameters, such as latency and throughput. Moreover, the saturation packet injection rate in WiNoC with four WRs is improved to about 33% under uniform traffic and is increased up to about 50% under the Bit-complement traffic pattern. This is increased by 16 and 50% in WiNoC with 16 WRs for uniform and Bit-complement traffic patterns, respectively, compared to the conventional WiNoCs.

Application of Logical Sub-networking in Congestion-aware Deadlock-free SDmesh Routing

An adaptive routing helps in evading early network saturation by steering data packets through the less congested area at the oppressive loaded situation. However, performances of adaptive routing are not always promising under all circumstances. Say for, given more freedom in choosing an alternate route on non-minimal paths for a substantially loaded network even may result in worsening network performances due to following longer route under adaptive routing. Here, underlying topology facilitates routing by offering more alternate short-cut routes on minimal or quasi-minimal paths. This work presents a congestion-aware (CA) adaptive routing for one-hop diagonally connected subnet-based mesh (SDmesh) network aiming to facilitate both performances and routing flexibility simultaneously. Our proposed technique on the selected system facilitates packet routing, offering more options in choosing an output link from minimal or quasi-minimal paths and hence helps in lowering packet delay by shortening the length of traversed traffic under the oppressive loaded situation. Furthermore, we have also employed a congestion-aware virtual input crossbar router aiming to split the entire network into two distinct logically separated sub-networks. It facilitates preserving important routing properties like deadlock, live-lock fairness, and other essential routing constraints. Experiments, conducted over two 8×8- and 12×12-sized networks, show an average improvement of 25--87.5% saturated latency and 60--83% throughput improvement under uniform traffic patterns for the proposed CA routing compared to centralized adaptive XY routing. Experimental results on application-specific PARSEC and SPLASH2 benchmark suites show an average of 22--50% latency and 23--30% throughput improvements by the proposed technique compared to centralized XY routing on the baseline mesh network. Moreover, experiments were also carried out to check the performance of the proposed routing method with different newly proposed deadlock-free adaptive routing approaches over the same subnet-based diagonal mesh (SDmesh) network and reported.

ECDR2: Error Corrector and Detector Relocation Router for Network-on-Chip

Network-on-chip (NoC) is commonly used in modern many-core systems due to their high bandwidth and flexibility. As the manufacturing process keeps scaling, the reliability challenge in NoCs increases as well. The error correction code (ECC) is widely adopted in error correction NoCs to improve the data correctness. At the same time, extra stages are introduced in the router pipeline to improve the error correction capability. As a result, conventional error correction routers suffer from high network latency. Motivated by this limitation, i.e., we remove the extra pipeline stages delicately introduced for error correction. We propose an error correction router, called error corrector and detector relocation router (ECDR2), whose architecture optimizes the pipeline flow of the router. As a result, it can achieve both low latency and high error correction.Experimental results show that, compared with the baseline design, ECDR $^{2}$ 2 obtains 13.67 and 39.4 percent less average latency under the uniform traffic pattern and Dedup benchmark, respectively, in an 8 × 8 mesh NoC. The circuit area of ECR is also 7.9 percent less than that of the baseline design under 45-nm technology.

Multidomain Inter/Intrachip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems

Rack-scale computing systems are promising to undertake the emerging large-scale applications by distributing massive tasks to processing cores. The communication and coordination efficiency of these tasks and resources directly affect the system performance and energy consumption. Silicon photonic interconnects are expected to address the communication and system power consumption challenges imposed on rack-scale systems. However, the control for optical interconnects can cause server performance degradation if not properly designed, especially for the complicated and time-consuming multidomain networks. In this paper, we study the optical interconnects for rack-scale computing systems and propose a new communication flow and control scheme for the efficient coordination of distributed resources. Particularly, we first propose a forward propagation strategy that parallels the path reservation process with the distributed tasks connection setup. Second, we develop a pre-emptive chain feedback (PCF) scheme to optimize multidomain path reservation. The PCF scheme pre-emptively allocates network resources with the help of multicell reservation window and quickly releases resources with a feedback mechanism. This solution increases the network resources utilization and task coordination efficiency while minimizing path reservation overheads. Comparing to the baseline InfiniBand network fabric and handshake scheme, PCF can improve network throughput greatly under uniform and hotspot traffic patterns. Realistic benchmark results show that the PCF scheme on average reduces 52% and 60% energy consumption per unit system performance than InfiniBand and the handshake scheme for a 256-node rack system.

Petascale: A Scalable Buffer-Less All-Optical Network for Cloud Computing Data Center

Optical packet switching is considered as a long-term solution for future data center networks due to their technological strengths, including high throughput, fine switching granularity, and excellent flexibility. However, most prior optical designs are either difficult to scale, costly to solve the packet collision, or inflexible to exploit the multiple wavelengths to increase the end-to-end connectivity. To this end, we present PETASCALE, a scalable, lossless, and high-performance optical data center network. By embedding full-mesh into a bipartite graph, PETASCALE is able to scale beyond 60 000 servers while achieving up to 2.5 and 2 times saving in a number of switches and cables, respectively, compared with fat tree topology. PETASCALE leverages the negative acknowledgment (NACK) and retransmission scheme to solve the packet collision, thus eliminating the complex and costly buffers. Then by leveraging a state retention mechanism, the contention can be notified over multiple hops in near real time. To further improve the bandwidth utilization, a wavelength routing algorithm is proposed to restrict the packet collision domain within the source pod. Moreover, PETASCALE designs a novel switch structure to support both the multi-hop NACK and wavelength routing. Our simulation results show that PETASCALE is able to reduce the end-to-end latency by more than 50% compared with an electrical fat tree network. For throughput, PETASCALE can deliver about 89% bisection bandwidth of a non-blocking network under uniform traffic pattern. While under the local traffic pattern, it can even achieve higher throughput than fat tree and other optical designs.

Low latency Path Aware XY-X Routing Algorithm for NoC Architectures

Route specific information with the SoC needs a great deal of wiring, which increases the Resistance & Capacitance (RC) component of the system. Network on Chip (NoC) is utilized as the interface to address the problems in SoC, On-chip interconnection network in NoC has gained more consideration over steadfast wiring and buses, like lower latency, scalability and high performance. Present routing algorithms in NoC is suffered from load balancing at incarnation networks under non-uniform traffic conditions, causes increase the NoC trade-offs (latency and throughput). Adaptive routing is a technique to progress the load balance, but previous adaptive routing techniques used uniform traffic patterns to form the routing decisions. This paper proposes a new approach at non- uniform traffic patterns in channel state and path specific, Path Aware Routing (PAR XY-X) uses a timeout piggybacking for acknowledgement and load shedding to avoid congestion which choose optimistic path calculation unit to connect the destination node without glue logic decisions in routing. PAR XY-X outperforms the Normal XY routing by 20% and 33% with respect to Avg.latency and throughput.

A shortest path routing mechanism based on ${S_3}$ for TriBA-Net

The routing algorithm of a Network-on-Chip (NoC) is essential to its performance and power consumption. This paper presents a novel shortest path routing algorithm for TriBA-Net. First, the algorithm designs a coding scheme based on the topological features of TriBA-Net. The set of words 1, 3, and 2, used in the coding scheme, has the same meaning as the well-known group ${S_3}$ on 3-letters. Second, a communication model, which contains 6 types of flow modes, has been proposed for reflecting the status of the path within two hops. Finally, the algorithm is simplified by the cyclic permutation characteristic of the ${S_3}$ group. Whats more, the implementation of the SPR4T router is completed under the XC6VLX550TL chip. Experimental results show that under the uniform traffic pattern in the 27-node TriBA-Net performance test, SPR4T routing algorithm has a 7.5% higher saturation injection rate and a 7.7% higher throughput rate, with the obvious savings of hardware overhead and lower power consumption when compared to the SPORT routing algorithm.

Design and evaluation of ZMesh topology for on-chip interconnection networks

This article presents the design and evaluation of a scalable and energy efficient Network-on-Chip topology with diagonal links, called ZMesh. A heuristic technique for mapping applications onto the ZMesh topology has been proposed. Further, a mapping technique based on particle swarm optimization combined with simulated annealing has also been considered for a fair comparison of the performance of ZMesh with that of other topologies. Experimental evaluation shows that ZMesh when compared with baseline Mesh, shows an average improvement of up to 1.25× and 1.20× in energy consumption and execution time, respectively while running real application traces. Compared to the state-of-the-art topologies such as DMesh, ZMesh shows an average improvement of up to 2.39× in terms of energy consumption, while suffering a degradation of up to 9.37% in execution time, for running real application traces. For the synthetic as well as real applications with more uniform traffic pattern, such as constant geometry algorithms, ZMesh achieves better energy efficiency than the other considered topologies. Evaluation of ZMesh for multicast kind of traffic using a proposed multicast routing algorithm shows improvement in link energy consumption by up to 55%, for the considered scenarios, as compared to unicast-based multicast routing.

Capacity of Social-Aware Wireless Networks With Directional Antennas

The widespread of smart phones has brought new social-aware features to wireless networks. Users prefer to forward traffic to their social contacts in social-aware networks, which is highly different from the traditional uniform traffic pattern. To this end, we analyze a social-aware wireless network, which is modeled by the social contacts between nodes, and explore its impact on network throughput capacity. We present that it can refine social contacts, thus improving the network capacity. Moreover, directional antennas are applied to further enhance the capacity performance, which can reduce the interference brought by other simultaneous communications. We derive the throughput capacity for social-aware networks with single-beam and multi-beam directional antenna, respectively. For single-beam directional antenna, we prove that when wireless networks are dominated by traffics of short-distance social contact, the throughput capacity can be promoted from order of $(\Theta ({1}/{\theta ^{2}}n\,\text {log}\,n)^{1/2})$ to $\Theta ({1}/{\theta ^{2} \text {log}\,n})$ . In addition, when the beamwidth $\theta $ is at order of $\Omega ({1}/{({\log {n}})^{1/2}})$ , the throughput capacity is a constant. Thus, the wireless network is scalable. For multi-beam antennas, we prove that when sidelobe gain $G_{s}$ is at order of $o(G_{m})$ , where $G_{m}$ is main lobe gain, compared with the single-beam case, the network capacity can achieve the order of $\Theta ({1}/{\theta ^{2}\text {log}\,n})$ .

Time-Division-Multiplexing–Wavelength-Division-Multiplexing-Based Architecture for ONoC

Future many-core processors will require high-performance yet energy-efficient on-chip networks to provide a communication substrate for the continually increasing number of cores on one chip. Optical networkon- chip (ONoC) is employed as a promising candidate interconnection solution for its high bandwidth and low energy consumption. However, optical circuit-switching (OCS) based architectures face the problem of high network congestion, low network utilization, and an overhead in power dissipation under heavy loads. In this paper, we propose an ONoC architecture with time-division multiplexing (TDM) and wavelength-division multiplexing (WDM) technology to solve the network contention problem faced by OCSbased ONoC. The number of wavelength groups and timeslots is optimized by using a genetic algorithm. A new optical router is designed to realize our TDM–WDM communication technology. A detailed model is built to analyze insertion loss and crosstalk noise. The simulation results show that TDM–WDM-based ONoC has better performance compared with equivalent OCS-mesh ONoC under a uniform traffic pattern. Similar analysis can be drawn for the real science application based on the PARSEC benchmark.

MRONoC: A Low Latency and Energy Efficient on Chip Optical Interconnect Architecture

The circuit switched optical network on chip (ONoC) is popularly employed since the optical buffer is not available. However, this technique suffers from limited transmission bandwidth, high setup-time overhead, and high network resource contention, which consequentially induces long latency and degraded throughput. In this paper, we propose a new ONoC architecture aiming at ultralow setup cost, improved scalability, and contention-free communication. We first utilize wavelength division multiplexing (WDM) to introduce the basic version of this ONoC with efficient wavelength assignment. A series of potential versions are developed by using multiple waveguides to relieve the pressure on the number of wavelengths. These potential versions can make a tradeoff between required wavelengths and waveguides and improve the scalability. The new architectures employ two layers relying on the interlayer coupler, which contributes to the decrease of crossing losses. The simulation results show that the architecture can achieve 133% saturated bandwidth improvement compared with the traditional mesh ONoC employing WDM technology under the uniform traffic pattern.

Mathematical modelling for TM topology under uniform and hotspot traffic patterns

ABSTRACTInterconnection networks are introduced when dealing with the connection of a significant number of processors in massively parallel systems. TM topology is one of the latest interconnection networks to solve the deadlock problem and achieve high performance in massively parallel systems. This topology is derived from a Torus topology with removing cyclic channel dependencies. In this paper, we derive a mathematical model for TM topology under uniform and hotspot traffic patterns to compute the average delay. The average delay is formulated from the sum of the average delay of network, the average waiting time of the source node and the average degree of virtual channels. The results obtained from the mathematical model exhibit a close agreement with those predicted by simulation. In addition, sufficient simulation results are presented to revisit the TM topology performance under various traffic patterns.

3D network-on-chip design for embedded ubiquitous computing systems

A novel 3D NoC topology for embedded ubiquitous computing is proposed.A minimal routing algorithm with path diversity in the 3D NoC Topology is used.A power efficient architecture design for NoC-based embedded ubiquitous computing is introduced. Ubiquitous High-Performance Computing applications, such as cyber-physical systems, sensor networks and virtual reality require the support of terascale embedded systems that can deliver higher performance than current systems. Multi-cores, many-cores and heterogeneous processors are becoming the typical design choices to satisfy these requirements. Inter core communication has been one of the major challenges as it affects the bandwidth and power consumption of the multi-cores processors. Network-on-Chips (NoCs) present a fast and scalable interconnection solution to fulfill the requirements of Ubiquitous High-Performance Computing applications. This paper proposes a novel 3D Network-on-Chip called Octagon for Ubiquitous Computing (OUC) that is designed for Embedded Ubiquitous Computing Systems. OUC provides low network diameter and path diversity. Simulation results show that the proposed topology achieves a significant decrease in latency and an average 21.54% and 12.89% improvement in average throughput under hotspot and uniform traffic pattern respectively.

Instantaneous communication capacities of vehicular ad hoc networks

Wireless communications among vehicles, roadside infrastructures, and traffic management centers can enable the development of next-generation Intelligent Transportation Systems so as to tackle basic traffic problems associated with driving safety, road congestion, and vehicle emissions. This paper analytically investigates the instantaneous communication capacities of vehicular ad hoc networks (VANETs), which measure the upper bounds of the message transmission rates of vehicles. Subject to interference among wireless transmissions, the broadcast capacity is defined by the maximum number of successful receivers, and the unicast capacity by the maximum number of successful senders. With the protocol communication model and uniform vehicular traffic patterns, we derive closed-form formulas for the capacities as functions of transmission range r, interference ratio δ, vehicular density ρ, and channel capacity W. We show that broadcast capacities are approximately W(2+δ)rρ+1 for uni-directional communications, and 2W(2+δ)rρ+1 for bi-directional communications; while unicast capacities are approximately W(1+δ)rρ+1 for uni-directional communications, and W(1+δ)rρ+1 for bi-directional communications. For general vehicular traffic patterns, an optimization model is proposed to calculate the capacities, and a genetic algorithm integrated with the protocol communication model is developed to solve the optimization problem. Finally, the impacts of different transmission ranges, interference ratios, and shock waves on communication capacities are analyzed.

An Optimum Value of Dynamic Communication Performance for Midimew Connected Mesh Network

A Midimew connected Mesh Network (MMN) is a proposed hierarchical interconnection network in which numerous basic modules are interconnected in a hierarchical fashion to construct a massively parallel computer. Here, the basic module is the first level of the network which is connected by mesh network while higher level network is connected by a midimew network. In this study, we have evaluated a dynamic communication performance of a variety of MMN using the TOPAZ simulator using a deadlock free routing algorithm with uniform traffic patterns, whereby the dimension order routing and virtual cut-through flow control are used. It is found that the saturation throughput of the Virtual MMN (VMMN) is higher than that of Horizontal MMN (HMMN), Symmetric MMN (SMMN), and Tori connected mESH network (TESH).

HTM: a new hierarchical interconnection network for future generation parallel computers

ABSTRACTIn this paper, we have discussed the architectural structure, static network performance, and dynamic communication performance of a new hierarchical interconnection network called hierarchical Tori connected mesh network (HTM). For the exploration of static network performance, we have evaluated degree, diameter, cost, average distance, arc-connectivity, bisection width, and wiring complexity. We have also evaluated the dynamic communication performance of HTM, its counter rival H3DM, and conventional mesh and torus networks using a deadlock-free dimension order routing using two virtual channels under uniform and non-uniform traffic patterns. The dynamic communication performance is evaluated using computer simulation. We discovered that the HTM has a number of lucrative properties. These include constant node degree, small diameter, low cost, small average distance, moderate (neither too low, nor too high) bisection width, and less wiring complexity. HTM also yields high throughput per link and very low zero load latency, which provide better dynamic communication performance than that of H3DM, mesh, and torus networks.

Heavy-Traffic Behavior of the MaxWeight Algorithm in a Switch with Uniform Traffic

We consider a switch with uniform traffic operating under the MaxWeight scheduling algorithm. This traffic pattern is interesting to study in the heavy-traffic regime since the queue lengths exhibit a multi-dimensional state-space collapse. We use a Lyapunov-type drift technique to characterize the heavy-traffic behavior of the expectation of the sum queue lengths in steady-state. Specifically, in the case of Bernoulli arrivals, we show that the heavy-traffic scaled queue length is ( n -- 3/2 + 1/2 n ). Our result implies that the MaxWeight algorithm has optimal queue-length scaling behavior in the heavy-traffic regime with respect to the size of a switch with a uniform traffic pattern. This settles the heavy-traffic version of an open conjecture.