Uniform Dielectric Layer Research Articles

Atomic Layer Deposition Growth and Characterization of Al2O3 Layers on Cu-Supported CVD Graphene

The deposition of thin uniform dielectric layers on graphene is important for its successful integration into electronic devices. We report on the atomic layer deposition (ALD) of Al2O3 nanofilms onto graphene grown by chemical vapor deposition onto copper foil. A pretreatment with deionized water (DI H2O) for graphene functionalization was carried out, and, subsequently, trimethylaluminum and DI H2O were used as precursors for the Al2O3 deposition process. The proper temperature regime for this process was adjusted by means of the ALD temperature window for Al2O3 deposition onto a Si substrate. The obtained Al2O3/graphene heterostructures were characterized by Raman and X-ray photoelectron spectroscopy, ellipsometry and atomic force and scanning electron microscopy. Samples of these heterostructures were transferred onto glass substrates by standard methods, with the Al2O3 coating serving as a protective layer during the transfer. Raman monitoring at every stage of the sample preparation and after the transfer enabled us to characterize the influence of the Al2O3 coating on the graphene film.

Tailoring amorphous boron nitride for high-performance two-dimensional electronics

Two-dimensional (2D) materials have garnered significant attention in recent years due to their atomically thin structure and unique electronic and optoelectronic properties. To harness their full potential for applications in next-generation electronics and photonics, precise control over the dielectric environment surrounding the 2D material is critical. The lack of nucleation sites on 2D surfaces to form thin, uniform dielectric layers often leads to interfacial defects that degrade the device performance, posing a major roadblock in the realization of 2D-based devices. Here, we demonstrate a wafer-scale, low-temperature process (<250 °C) using atomic layer deposition (ALD) for the synthesis of uniform, conformal amorphous boron nitride (aBN) thin films. ALD deposition temperatures between 125 and 250 °C result in stoichiometric films with high oxidative stability, yielding a dielectric strength of 8.2 MV/cm. Utilizing a seed-free ALD approach, we form uniform aBN dielectric layers on 2D surfaces and fabricate multiple quantum well structures of aBN/MoS2 and aBN-encapsulated double-gated monolayer (ML) MoS2 field-effect transistors to evaluate the impact of aBN dielectric environment on MoS2 optoelectronic and electronic properties. Our work in scalable aBN dielectric integration paves a way towards realizing the theoretical performance of 2D materials for next-generation electronics.

Novel polymer/bio-filler composites as alternative eco-friendly materials for energy storage: From solution behavior to solid state analysis

To combat the issue of plastics contamination of the medium, the current technologies are aiming towards development of green materials that are substituting the harmful elements from the disposed devices. This article opens a fresh perspective on designing novel polymer composites by loading hydroxypropyl methylcellulose (HPMC) with bio-derived filler or a mixture of bio-filler and barium titanate (BT) to make alternative eco-compatible materials for energy storage. New insights are extracted from a detailed analysis that correlates the solution behavior to solid state analysis. Rheological data evidence that for attaining uniform dielectric layers spinning times beyond 100 s and spinning speeds below 80 rpm are required. Interfacial compatibility with metal electrodes is checked via experiments of sample wetting on silver or gold layer, showing that adhesion work is increased of 6.24 times for gold support and 5.63 times for silver support, being adequate for capacitor applications. The sample morphology was recorded by scanning electron microscopy, indicating good dispersion of the filler or filler mixture in the bulk cellulose derivative matrix. Refractometry experiments revealed an enhancement of molecular polarizability upon loading, which led to increase of refractive index from 1.52 for neat HPMC to 1.56 for HPMC/oat 40 and 1.57 for HPMC/oat + BT 40, at 489 nm. This is reflected in the increase of the dielectric constant at 1 KHz, namely: 2.19 (HPMC) to 2.79 (HPMC/oat 40) and 3.36 (HPMC/oat + BT 40). The dielectric breakdown is slightly lowered upon loading from 43.8 ∙106 V/m (matrix) to 42.3∙106 V/m (HPMC/oat 40) and 42.0∙106 V/m (HPMC/oat + BT 40). The resulted electric energy density values reach at highest loading the values of 2.198∙104 J/m3 for the sample with oat and 2.635∙104 J/m3 for the sample with oat and BT. This work is a fresh initiative of making eco-compatible dielectrics for future storage systems.

Wafer-scale organic-on-III-V monolithic heterogeneous integration for active-matrix micro-LED displays.

The organic thin-film transistor is advantageous for monolithic three-dimensional integration attributed to low temperature and facile solution processing. However, the electrical properties of solution deposited organic semiconductor channels are very sensitive to the substrate surface and processing conditions. An organic-last integration technology is developed for wafer-scale heterogeneous integration of a multi-layer organic material stack from solution onto the non-even substrate surface of a III-V micro light emitting diode plane. A via process is proposed to make the via interconnection after fabrication of the organic thin-film transistor. Low-defect uniform organic semiconductor and dielectric layers can then be formed on top to achieve high-quality interfaces. The resulting organic thin-film transistors exhibit superior performance for driving micro light emitting diode displays, in terms of milliampere driving current, and large ON/OFF current ratio approaching 1010 with excellent uniformity and reliability. Active-matrix micro light emitting diode displays are demonstrated with highest brightness of 150,000 nits and highest resolution of 254 pixels-per-inch.

Multimodal antireflective coatings for perfecting anomalous reflection from arbitrary periodic structures

Metasurfaces possess vast wave-manipulation capabilities, including reflection and refraction of a plane wave into non-standard directions. This requires meticulously-designed sub-wavelength meta-atoms in each period of the metasurface which guarantee unitary coupling to the desired Floquet-Bloch mode or, equivalently, suppression of the coupling to other modes. Herein, we propose an entirely different scheme to achieve such suppression, alleviating the need to devise and realize such dense scrupulously-engineered polarizable particles. Extending the concept of anti-reflective coatings to enable simultaneous manipulation of multiple modes, we show theoretically and experimentally that a simple superstrate consisting of only several uniform dielectric layers can be modularly applied to \textit{aribtrary} periodic structures to yield perfect anomalous reflection. This multimodal anti-reflective coating (MARC), designed based on an analytical model, presents a conceptually and practically simpler paradigm for wave-control across a wide range of physical branches, from electromagnetics and acoustics to seismics and beyond.

Analysis of Deep Learning-Based Phase Retrieval Algorithm Performance for Quantitative Phase Imaging Microscopy.

Quantitative phase imaging has been of interest to the science and engineering community and has been applied in multiple research fields and applications. Recently, the data-driven approach of artificial intelligence has been utilized in several optical applications, including phase retrieval. However, phase images recovered from artificial intelligence are questionable in their correctness and reliability. Here, we propose a theoretical framework to analyze and quantify the performance of a deep learning-based phase retrieval algorithm for quantitative phase imaging microscopy by comparing recovered phase images to their theoretical phase profile in terms of their correctness. This study has employed both lossless and lossy samples, including uniform plasmonic gold sensors and dielectric layer samples; the plasmonic samples are lossy, whereas the dielectric layers are lossless. The uniform samples enable us to quantify the theoretical phase since they are established and well understood. In addition, a context aggregation network has been employed to demonstrate the phase image regression. Several imaging planes have been simulated serving as input and the label for network training, including a back focal plane image, an image at the image plane, and images when the microscope sample is axially defocused. The back focal plane image plays an essential role in phase retrieval for the plasmonic samples, whereas the dielectric layer requires both image plane and back focal plane information to retrieve the phase profile correctly. Here, we demonstrate that phase images recovered using deep learning can be robust and reliable depending on the sample and the input to the deep learning.

High-k BaTiO3 nanoparticle films as gate dielectrics for flexible field effect transistors

Highly uniform dielectric and semiconductor layers were incorporated from nanoparticle inks into flexible transparent field-effect transistors (FETs). The FETs showed superior performance characteristics, being promising for the development of silicon-free based electronics.

Stress induced potential barriers in composite piezoelectric semiconductor fibers in extension

We study the extension of composite fibers with piezoelectric dielectric layers and nonpiezoelectric semiconductor layers. A theoretical analysis is performed using the one-dimensional macroscopic model of piezoelectric semiconductor fibers. An analytical solution is obtained for a fiber with a uniform nonpiezoelectric semiconductor layer and piecewise uniform piezoelectric dielectric layers. Numerical results show that an electric potential barrier forms near the junction between the piecewise uniform piezoelectric layers. The potential barrier depends on the extensional stress. It may be used to manipulate the electrical behaviors such as the conduction in the fiber mechanically and thus has potential applications in piezotronics.

Fabrication and characterization of quasi-three-dimensional capacitor structure based on carbon nanowalls

Vertically oriented graphene structures have a high specific surface area which makes them potential candidates for realization of various devices. On their basis, supercapacitors, lithium-ion batteries, absorbing coatings and bolometers, gas and electrochemical sensors, and other devices have been demonstrated. At the same time, such structures for conventional capacitors remain unexplored. In this research the fabrication technology of quasi three-dimensional capacitors based on metal/carbon nanowalls/insulator/metal structure (MCNWIM) are demonstrated. Carbon NanoWalls (CNWs) were used as a base electrode to increase the specific surface area of capacitors. Uniform dielectric and metal layers of aluminum oxide (AlOx) and titanium nitride (TiNx) were deposited by thermal atomic layer deposition (ALD) and plasma-enhanced atomic layer deposition (PEALD). A comparative analysis of capacitors with and without a carbon nanostructure has been performed. The influence of dielectric thickness on the capacitance density as well as dependencies of breakdown voltage on the surface area were experimentally observed. The maximum capacitance density was 3.6 μF/cm2 at the AlOx thickness of 10 nm, which is 4.7 times higher than the values of capacitors without carbon nanostructure. The investigated structures were manufactured on four-inch silicon wafers that provide the possibility of the mass production of capacitors based on CNWs.

Smart Design of Resistive Switching Memory by an In Situ Current‐Induced Oxidization Process on a Single Crystalline Metallic Nanowire

AbstractResistive switching random access memory (ReRAM) has recently generated significant interest due to its potentials used in nanoscale logic, memory devices, and neuromorphic applications. From the device physics, a uniform dielectric layer is necessary to access as the main switching layer to perform stable resistive switching. This, however, makes the fabrication process more challenging. In this regard, a design of resistive switching memory by an in situ current‐induced oxidization process on a single crystal metallic nanowire (NW) is demonstrated where a single crystal Cu NW is found as the best material with stable switching behaviors after the in situ current‐induced oxidization process. With the in situ current‐induced oxidization process by high current density on the Cu NW, a reversible resistive switching up to 100 cycles with a large ON/OFF ratio of &gt;103 and a low switching voltage of &lt;0.5 V can be obtained. The initial current‐induced oxidation provides a core–shell (Cu2O/Cu) nanowire structure that contributed to the switching properties. The possible switching mechanisms and potential guidelines are systematically proposed. The current work opens up the opportunities to design the ReRAM device with full‐ metallic materials.

A chemisorbed interfacial layer for seeding atomic layer deposition on graphite.

The integration of graphene, and more broadly two-dimensional materials, into devices and hybrid materials often requires the deposition of thin films on their usually inert surface. As a result, strategies for the introduction of surface reactive sites have been developed but currently pose a dilemma between robustness and preservation of the graphene properties. A method is reported here for covalently modifying graphitic surfaces, introducing functional groups that act as reactive sites for the growth of high quality dielectric layers. Aryl diazonium species containing tri-methoxy groups are covalently bonded (grafted) to highly oriented pyrolytic graphite (HOPG) and graphene, acting as seeding species for atomic layer deposition (ALD) of Al2O3, a high-κ dielectric material. A smooth and uniform dielectric film growth is confirmed by scanning electron microscopy (SEM), atomic force microscopy (AFM) and electrical measurements. Raman spectroscopy showed that the aryl groups gradually detach from the graphitic surface during the Al2O3 ALD process at 150 °C, with the surface reverting back to the original sp2-hybridized state and without damaging the dielectric layer. Thus, the grafted aryl groups can act as a sacrificial seeding layer after healing the defects of the graphitic surface with annealing treatment.

Influence of Mg ion concentration in ZrO2 gate dielectric layered silicon based MOS capacitors for memory applications: Thorough understanding of conduction processes

Various high-κ metal-oxide-semiconductor (MOS) capacitors with different concentrations of Mg doped ZrO2 (Mg:ZrO2) gate dielectric on p-type silicon (100) substrates were fabricated by using electron beam evaporation. A uniform and crack free dielectric layers of Mg:ZrO2 having RMS surface roughness in the range from 0.25 to 0.83 nm were achieved. The dielectric layers were structurally and electrically studied. Structural analysis from GIXRD and Williamson-Hall plots revealed that Mg incorporation into ZrO2 lattice has stabilized the tetragonal phase and the residual strain in the tetragonal stabilized Mg:ZrO2 layers had increased with increasing Mg concentration. Elemental composition studies of different layers in the MOS capacitors using Rutherford backscattering spectrometry (RBS) revealed the presence of very thin, unintentional and non-stoichiometric SiOx interfacial layer between dielectric and semiconductor interfaces. Thickness of the Mg:ZrO2 dielectric layers in the MOS capacitors measured by using RBS and cross-sectional field-emission scanning electron microscopy was in the range from 44.7 to 96.6 nm. A high dielectric constant of 29.8 with the equivalent oxide thickness of 6.5 nm was achieved in the 5 mol% Mg:ZrO2 dielectric layer. The hysteresis in the C-V characteristics of the MOS capacitors has been explained in detail based on the interactions of Mg ions with oxygen vacancies in the dielectric layer. Various conduction mechanisms have been elucidated to explain the leakage currents in the MOS capacitors. The decrease in Schottky and Poole-Frenkel barrier heights at the lower voltages (0 to − 3V) was found responsible for the increase in the leakage current as the Mg ion concentration was increased. Space charge limited conduction mechanism has been found to be dominant in larger applied voltage region (− 3V to − 10V). The Fowler-Nordheim tunneling and trap-assisted tunneling were dominant at the higher negative voltage regions greater than − 10V.

Developement of Printed OTFTs and Logic Circuits

We report the development of inkjet-printed organic thin-film transistors (OTFTs), inverters and logic circuits on PET substrate. The mobility of 1 cm2/Vs and 0.1 cm2/Vs achieved on p-type and n-type printed OTFTs with an operation voltage of 15 V. The printed uniform and thin dielectric layer achieved by introducing coffee ring effect on printing process. A gain value of 24 obtained from the printed CMOS inverter and the device exhibits an excellent air-stability without encapsulation. Our results demonstrated the potential of the developed printed transistors for flexible electronics in the near future.

Inkjet printed thin and uniform dielectrics for capacitors and organic thin film transistors enabled by the coffee ring effect

The deposition of a thin and uniform dielectric layer is required for high performance printed capacitors and thin film transistors (TFTs), however this is difficult to achieve with printing methods. We have demonstrated inkjet-printed dielectrics with a uniform thickness from 70 nm to 200 nm by taking advantage of the coffee ring effect. A high capacitance per unit area of 230 pF/mm2 is achieved from capacitors with linear morphologies fully printed onto flexible substrates. We also demonstrate organic TFTs with an average mobility of 0.86 cm2/Vs and a source drain current of 57 μA obtained with a supply voltage of 15 V. This performance was shown to be consistent, with a standard deviation of 15% obtained from hundreds of printed organic TFTs on PET substrates. This consistency was further validated by the production of functional NAND, NOR, AND and OR logic gates. Our results demonstrate that the coffee ring effect, which is usually viewed as undesirable, can enable higher performance in printed electronic devices.

Anisotropic reflection oscillation in periodic multilayer structures of parity-time symmetry.

We show that periodic multilayer structures with parity-time (PT) symmetries imposed by a balanced arrangement of gain and loss can exhibit anisotropic reflection oscillation patterns as the number of unit-cells is increasing. At the minima of reflection oscillation patterns, the PT symmetric medium exhibits bidirectional transparency with the eigenvalues of the scattering matrix degenerated, where the PT symmetric set-up can still render directional responses due to the one-way field localization inside the system. With certain number of unit-cells, the PT symmetric crystal is unidirectionally invisible. More complicated reflection/transmission oscillations can be observed by segregating neighboring unit-cells with a uniform dielectric layer. Our results may pave the way towards a new class of functional optical devices with intriguing and unexpected directional responses.

Resonance shifts of transverse-electric whispering gallery modes in a spheroidal resonator

A variational method was applied to find the wave function of a transverse-electric whispering gallery mode (WGM) in a spheroidal resonator of a uniform refractive index (RI). It was found that the electric field is tangential to the resonator surface as in the sphere, up to the linear order of the ellipticity. Using the wave function, the resonance shift due to adsorption of a thin, uniform dielectric layer onto the surface and the shift by a uniform RI change in the surroundings were evaluated in the perturbation theory. The shift by the RI change is not affected by the ellipticity, but the shift by the layer adsorption now depends on the meridional order. However, the correction is not large unless the ellipticity is large and the meridional order is away from the one for the equatorial mode of WGM.

Optical properties of two-layer one-dimensional magneto-plasmonic crystals

This paper discusses the optical properties of magneto-plasmonic crystals, which are one-dimensional metallic gratings deposited on a uniform magnetic dielectric layer. All possible cases of the orientation of the magnetization are investigated. The resonance features in the spectra of magnetooptic effects are explained in terms of the excitation of the intrinsic waves of the system: surface plasmon–polaritons and quasi-waveguide modes of the dielectric layer.

Electrowetting on a dielectric surface roughened with zinc oxide tetrapod nanocrystals

Changing the contact angle between a solid substrate and a droplet with an external voltage is important in the field of microfluidics. On a flat surface, the range of the reversible contact angle is about 90°: from 30° to 120°. However, on a rough surface, such as superhydrophobic surface of carbon nanotube, carbon nanofibers, silicon nanowires, ZnO nanorods, etc., the reverse transition from the Wenzel state to Cassie state is usually prevented due to an energy barrier resulting in a lower contact angle range. In this paper, we described the electrowetting on a rough surface of ZnO tetrapods. The contact angle on ZnO tetrapod was as high as 155°, and a wide range of reversible contact angles actuated by an electric potential was observed. Electrolysis, which was a problem in previous research of nano-structured superhydrophobic surface, was avoided by applying a uniform dielectric layer between the conductive ITO and the ZnO tetrapods. The proposed method has potential applications in microfluidics devices with a large dynamic range of capillary force.

Atomic-Layer-Deposited Al2O3 as Gate Dielectrics for Graphene-Based Devices

We present a facile route to deposit a uniform Al2O3 layer on a highly oriented pyrolytic graphite (HOPG) surface using atomic layer deposition (ALD). Al2O3 layers deposited from TMA (trimethylaluminum)/ H2O chemistry showed selective deposition only on step edges. However, TMA/O3 chemistry resulted in the deposition of Al2O3 layers on basal planes of HOPG, which has a chemically inert surface. An O3-pretreatement followed by Al2O3 deposition using TMA/O3 chemistry produced conformal and uniform Al2O3 dielectric layers with a small RMS roughness of ~ 0.2 nm. This suggests that O3-pretreatement prior to ALD deposition makes the chemically inert HOPG surface reactive toward ALD precursors, which leads to the desired two-dimensional growth mode. High-resolution transmission electron microscopy (HR-TEM) and Raman spectroscopy revealed that this O3 process used for Al2O3 deposition does not introduce a significant defect concentration to the top graphene layer. The dielectric constant of the deposited Al2O3 film on top of the HOPG surface was found to be ~ 9 from C-V measurements.

Ink-Jet-Printed Organic−Inorganic Hybrid Dielectrics for Organic Thin-Film Transistors

Using a thermally crosslinkable organosiloxane-based organic−inorganic hybrid material, we formulated a functional ink suitable for ink-jet printing of dielectric thin films. Ink solvent chemistry plays an important role in producing a uniform dielectric layer. In particular, the hydrodynamic motion of the solvents is controlled during the drying period. We used a higher-boiling-point solvent in order both to prevent a nozzle from clogging and to suppress convective flow. We also incorporated a lower-boiling-point solvent of high surface tension for diminishing the outward Marangoni flow. We successfully applied the printed hybrid dielectric layer with smooth surface morphology to the gate dielectric layer for organic thin-film transistors and analyzed the electrical performance of the transistor based on the ink-jet-printed dielectric layer, comparing with that of the transistor based on the spin-coated dielectric layer.