Uniformity Of Device Characteristics Research Articles

Carbon Nanotube Thin Films for High-Performance Flexible Electronics Applications.

Carbon nanotube thin films have attracted considerable attention because of their potential use in flexible/stretchable electronics applications, such as flexible displays and wearable health monitoring devices. Due to recent progress in the post-purification processes of carbon nanotubes, high-purity semiconducting carbon nanotubes can be obtained for thin-film transistor applications. One of the key challenges for the practical use of carbon nanotube thin-film transistors is the thin-film formation technology, which is required for achieving not only high performance but also uniform device characteristics. In this paper, after describing the fundamental thin-film formation techniques, we review the recent progress of thin-film formation technologies for carbon nanotube-based flexible electronics.

Wafer-Scale Fabrication of Recessed-Channel PtSe2 MOSFETs With Low Contact Resistance and Improved Gate Control

Wafer-scale fabrication of PtSe2 MOSFETs was demonstrated by photolithography on Pt films directly selenized at 400 °C. Taking advantage of the unique property of PtSe2 to transition from a semiconductor to a semimetal as its thickness increases beyond a few monolayers, channel recess was adapted for improving gate control while keeping the contact resistance below 0.01 $\Omega \cdot \text {cm}$ . The wafer-scale fabrication resulted in uniform device characteristics so that average instead of best results was reported. For example, the drain currents at ${V}_{\text {GS}} = -10$ V, ${V}_{\text {DS}} = -1$ V were $25~\pm ~5$ , 57 ± 8, and $618~\pm ~17~\mu \text{A}/\mu \text{m}$ for 4-, 8-, and 12-nm-thick PtSe2, respectively. The corresponding peak transconductances were 0.20 ± 0.1, 0.60 ± 0.05, and $1.4~\pm ~0.1~\mu \text{S}/\mu \text{m}$ . The forward-current cutoff frequency of 12-nm-thick PtSe2 MOSFETs was 42 ± 5 MHz, whereas the corresponding frequency of maximum oscillation was 180 ± 30 MHz. These results confirmed the application potential of PtSe2 for future-generation thin-film transistors.

Process Uniformity and Challenges of AlGaN/GaN MIS-HEMTs on 200-mm Si (111) Substrates Fabricated with CMOS-Compatible Process and Integration

We report the device characteristics and uniformity of AlGaN/GaN MIS-HEMTs fabricated on a full 200-mm (8-in) GaN-on-Si substrate using CMOS-compatible non-Au and non-lift-off-based fabrication process. An IDmax and gm of 387 mA/mm and 82 mS/mm were, respectively, measured across a 200-mm wafer. We have observed a good uniformity of device characteristics, namely ID (average 345 mA/mm; %σ of 5%), gm (average of 82 mS/mm; %σ of 4.9%), Rd (average of 10.2 Ω mm; %σ of 8.3%) and Vbr (average of 277 V, %σ of 17%) for AlGaN/GaN MIS-HEMTs grown on a 200-mm silicon substrate. For wafer line-yield, a very low wafer breakage (2%) was observed.

Effect of source/drain overlap region on device performance in a‐IGZO thin‐film transistors

Abstract— In this paper, the effect of source/drain overlap length on the amorphous indium gallium zinc oxide (a‐IGZO) TFT performance has been investigated. Results of this paper show that as source/drain overlap length decreases to a negative value forming S/D offset, the threshold voltage and S parameters of a‐IGZO TFTs increased and the field‐effect mobility decreased. The VT variation increases sharply as the channel length decreases because of the large resistance Roffset when it is formed at a‐IGZO source/drain. In the experiment, Roffset of each 1 μm, evaluated from the transfer length method (TLM), shows approximately 54–66 kΩ. This means thatthe source/drain overlap length is a very important control parameter for uniform device characteristics of a‐IGZO TFTs.

Device characteristics of AlGaAs/InGaAs HEMTs fabricated by inductively coupled plasma etching

Passivated 0.15-μm pseudomorphic high electron mobility transistors are fabricated by combining a wide head T-shaped gate using a dose split method of electron beam lithography and a highly selective and uniform inductively coupled plasma (ICP) recess process. The good DC uniformity was obtained across 4-inch wafer and the uniformity of maximum extrinsic transconductance and threshold voltage are 1.3 and 2.9%, respectively. The obtained uniform device characteristics are attributed to the gate recess etch process with the uniformity less than 5% by the ICP gate recess process. The maximum extrinsic transconductance was 568 mS mm −1. The cut-off frequency and maximum oscillation frequency were 90 and 160 GHz, respectively. The noise figure minimum measured at 28 GHz was 0.93 dB with associated gain of 10.03 dB. At 40 GHz, F min is 1.3 dB with G a of 8.33 dB.

Submicron RIE recessed InGaP/InGaAs doped-channel FETs

High performance submicron In/sub 0.49/Ga/sub 0.51/P/In/sub 0.15/Ga/sub 0.85/As doped-channel heterostructure field effect transistors (HFETs) have been developed and characterized. In order to achieve a high uniformity of device characteristics crossing the wafer, BCl/sub 3/+CHF/sub 3/ reactive ion etching technology in gate-recessed process is applied to fabricate the InGaP/InGaAs doped-channel FETs. The unity current gain cut-off frequency (f/sub T/), maximum frequency of oscillation (f/sub max/), and threshold voltage have been investigated versus the gate-length. The improved microwave performance in smaller gate-length devices is mainly associated with the reduction of the input capacitance. The 0.2 /spl times/ 200-/spl mu/m/sup 2/ gate-dimension DCFET exhibits a saturated P/sub out/ of 18.9 dBm, a power density of 388 mW/mm, a PAE of 35%, and an associated gain of 14 dB at 2.4 GHz.

Long-Pulse Duration Excimer Laser Processing in the Fabrication of High Performance Polysilicon TFTs for Large Area Electronics

AbstractIn this work, was investigated both numerically and experimentally, the excimer laser processing of a-Si films deposited on SiO2-coated glass substrates, using the very large area (∼ 20 cm2) and long pulse duration (200 ns) excimer source from SOPRA Company. Experiments were carried out in air or in neutral atmosphere, using both the single- and multi-shot mode. From the microstructural analysis of the laser irradiated area the formation of a large-grained material through the so-called SLG regime was evidenced. In addition, the application of a multi-shot process was demonstrated to be very efficient to prepare uniform polysilicon layers with enlarged grain sizes (up to 1.5 µm after 20 shots). Finally, poly-Si TFTs prepared in the optimized conditions (multi-shot, neutral ambience) exibited field effect mobilities up to 235 cm2/V.s (for N-type) and 84 cm2/V.s (for P-type), with fairly uniform device characteristics over large area and excellent stability under electrical stress.

Wavelength-selectable microarray light sourcesof multiple rangessimultaneously fabricated on single wafer

The authors have simultaneously fabricated multi-range wavelength-selectable light-sources (WSLs) on a single wafer by using microarray selective epitaxy (MASE). Compact (1.136 mm2) WSLs, each consisting of monolithically integrated eight-stripe microarray distributed-feedback laser diodes (DFB-LDs), an 8 × 1 multimode-interference (MMI) optical combiner, a semiconductor optical amplifier (SOA), and an electroabsorption (EA) modulator, showed an addressable wavelength range of ~15 nm with uniform device characteristics. A 47 nm-wide wavelength range was completely covered by three simultaneously fabricated WSLs.

1.55-μm wavelength-selectable microarray DFB-LD's with monolithically integrated MMI combiner, SOA, and EA-modulator

We developed compact (1.136 mm/sup 2/) eight-channel wavelength-selectable microarray distributed feedback laser diodes (DFB-LD's) with a monolithically integrated 8/spl times/1 multimode-interference (MMI) optical combiner, a semiconductor optical amplifier (SOA), and an electro-absorption (EA) modulator. By using /spl plusmn/10/spl deg/C thermal tuning, an addressable wavelength range of 15.3 nm with uniform device characteristics and 2.5-Gb/s modulation performance were successfully demonstrated.

Laser Processing of Polysilicon Thin-Film Transistors: Grain Growth and Device Fabrication

Pulsed excimer-laser processing of amorphous silicon on non-crystalline substrates is an important processing technology for large-area polysilicon electronics, such as flat-panel displays and two-dimensional imaging arrays. It also allows for the integration of amorphous silicon and polysilicon devices on the same glass substrate and provides procedures for the doping of self-aligned thin-film transistors. Materials studies show that laser-crystallized polysilicon exhibits a narrow peak in the average grain size as a function of the excimer laser energy density, with a corresponding peak in the electron mobility. This is of particular significance for devices since large grains imply high electron mobility. On the other hand, the peak in the grain size is very narrow and is also accompanied by a peak in the surface roughness of the film. These relationships force a compromise between large grain size for high mobility and homogeneous size distribution for uniformity of device characteristics. A window exists in process parameter space where good-quality devices with uniform characteristics have been obtained. Also, laser-processing enhancements, such as laser doping and fabrication of self-aligned transistors, provide additional tools to fabricate unique devices.

Low-threshold strained multi-quantum well lasers fabricated by selective metalorganic vapor phase epitaxy without a semiconductor etching process

Strained InGaAsP multi-quantum well (MQW) buried hetero- (BH) laser diodes (LDs) on a p-InP substrate were fabricated by selective metalorganic vapor phase epitaxy (MOVPE). In the laser fabrication process, both the strained MQW active layer and current blocking structure were directly formed by selective MOVPE without a semiconductor etching process. This novel laser fabrication process produces extremely uniform device characteristics that are essential to the deployment of optical subscriber systems. Furthermore, important device design parameters (e.g. the active stripe shape or the leakage current path configuration) are precisely controlled by only the epitaxial growth steps. This highly controllable laser fabrication method results in a very low-threshold current with excellent uniformity (Ith = 1.78 ± 0.19 mA) for 20 consecutive LDs (L = 200 μm with 70%–90% coatings).

Laser Crystallized Polysilicon Thin Films and Applications

AbstractPulsed excimer-laser crystallization of amorphous silicon on non-crystalline substrates is an important processing technique for large-area polycrystalline silicon films and devices. Interest stems, in large part, from proposals to use polycrystalline silicon on glass in large-area electronic applications, such as flat-panel active matrix displays and two-dimensional imaging systems. The polycrystalline silicon is envisioned to increase the functionality and reduce costs over the current circuits that use amorphous silicon. Also, it is found that laser-crystallized polycrystalline silicon exhibits some interesting materials properties, such as a sharp peak in the average grain size with large lateral grain growth as a function of excimer laser energy density. The average grain size increases with increasing laser fluence and peaks on the order of several microns or two orders of magnitude larger than the film thickness. The grain size then decreases with further increases in laser fluence. This peak in grain size is accompanied by a similar peak in the Hall electron mobility. This is a significant relationship for devices since the grain structure has a substantial influence on electrical properties. But to the detriment of device parameters, this large lateral grain growth occurs over a very arrow range of laser fluences and is accompanied by a corresponding peak in the surface roughness of the films. These relationships between laser processing conditions, materials properties, and device parameters force a compromise between large grain size for high mobility and homogeneity of material for uniformity of device characteristics. A window does exist in process parameter space where good-quality devices with uniform characteristics have been obtained. In addition, these attributes have been achieved under conditions that yield good polycrystalline silicon and good amorphous silicon devices on the same wafer within a mm of one another, allowing for hybrid polycrystalline and amorphous silicon circuits.

Polarization-insensitive semiconductor optical amplifier array grown by selective MOVPE

Polarization-insensitive 1.3 μm wavelength semiconductor optical amplifier (SOA) arrays are developed for the first time, by using a new fabrication process with selective MOVPE. In a four-channel array, the SOAs have uniform device characteristics of more than 20 dB signal gain and less than 1 dB polarization sensitivity.

4*4 GaAs/AlGaAs optical matrix switches with uniform device characteristics using alternating Delta beta electrooptic guided-wave directional couplers

Integrated 4*4 GaAs/AlGaAs optical matrix switches constructed from 12 electrooptic directional couplers have been realized. In order to achieve uniform device characteristics, molecular beam epitaxy and reactive ion beam etching were chosen as the crystal growth technique and waveguide fabrication technique, respectively, in addition to the simplified tree structure as a matrix switch architecture. As a result, matrix switches with quite uniform device characteristics, such as small switching voltage deviation and little path dependence in +or-0.5-dB propagation loss, have been realized. >

Giga-bit rate receiver OEICs grown by OMVPE for long-wavelength optical communications

Receiver optoelectronic integrated circuits (OEICs) in which AlInAs/GaInAs HEMTs and GaInAs pin PDs were integrated monolithically on InP substrates, were studied. Good uniformity of device characteristics over a 2-inch whole wafer was obtained. Three different types of receiver circuits, i.e. high-impedance type, trans-impedance type, and straightforward termination type, were fabricated and are discussed. The sensitivity of −30.4 dBm was obtained for 1.2 Gbit/s NRZ signals from the high-impedance type OEIC, into which an equaliser was also integrated. The receiver operated up to 1.6 Gbit/s. The dynamic range of more than 23 dB was obtained using the straightforward termination type OEIC. These performances are good enough for practical use in optical communication systems operating at gigabit/s data rates.

Noise-margin limitations on gallium-arsenide VLSI

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits will be needed to extend circuit complexity to the range currently dominated by silicon.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

GaAs digital IC technology/statistical analysis of device performance

A new approach to the design and fabrication of GaAs digital integrated circuits capable of high speed and low power dissipation has been demonstrated. This technology relies on Schottky-diode FET logic (SDFL) circuits which take advantage of the high switching speed of Schottky diodes and the high transconductance of the GaAs 1-µm gate MESFET. These circuits are fabricated by localized implantations directly into the semi-insulating GaAs substrate. Excellent results in terms of speed and power dissipation have been achieved, while circuit complexity has lrapidly grown as demonstrated by the successful operation of an eight-channel multiplexer, an eight-channel demultiplexer, and a 3 × 3 parallel multiplier employing 64, 60, and 75 gates, respectively. This rapid progress requires considerable work in monitoring the process through statistical evaluation of test devices. This paper discusses the process monitoring work carried out in support of the technology, The organization of the masks used for circuit development is described, with emphasis on process monitoring test patterns. Automatic instrumentation used to gather a large amount of statistical information is described, and wafer maps illustrating statistical results are presented and discussed. Uniformity of device characteristics over the full wafer and over smaller areas (circuit size) is compared. Implications of these results are discussed in terms of circuit yield.

MP-A3 GaAs digital IC technology/Statistical analysis of device performance

A new approach to the design and fabrication of GaAs digital integrated circuits capable of high speed and low power dissipation has been demonstrated. This technology relies on Schottky-diode FET logic (SDFL) circuits which take advantage of the high switching speed of Schottky diodes and the high transconductance of the GaAs 1-µm gate MESFET. These circuits are fabricated by localized implantations directly into the semi-insulating GaAs substrate. Excellent results in terms of speed and power dissipation have been achieved, while circuit complexity has lrapidly grown as demonstrated by the successful operation of an eight-channel multiplexer, an eight-channel demultiplexer, and a 3 × 3 parallel multiplier employing 64, 60, and 75 gates, respectively. This rapid progress requires considerable work in monitoring the process through statistical evaluation of test devices. This paper discusses the process monitoring work carried out in support of the technology, The organization of the masks used for circuit development is described, with emphasis on process monitoring test patterns. Automatic instrumentation used to gather a large amount of statistical information is described, and wafer maps illustrating statistical results are presented and discussed. Uniformity of device characteristics over the full wafer and over smaller areas (circuit size) is compared. Implications of these results are discussed in terms of circuit yield.

GaAs field-effect transistors with ion-implanted channels

Schottky-barrier-gate n channel depletion-mode field-effect transistors have been fabricated in GaAs by the use of sulphurion implantation directly into semi-insulating Cr-doped substrates to produce the channel. This technique eliminates the need for the growth of a thin epitaxial layer, as is usually done, and results in better uniformity of device characteristics over the wafer area. Performance of these devices at 1 to 12 GHz is described, and low-frequency characteristics are given.

The Semiconductor Fast-Neutron Dosimeter-Its Characteristics and Applications

The characteristics and most recent results with a semiconductor fast-neutron dosimeter are dTscribed. This device is a wide-base silicon n+ - p - p+ junction whose forward resistance is controlled by the density of injected charge carriers in the base region. The injected carrier density profile is a function of the carrier diffusion length. Upon neutron bombardment, the diffusion length is decreased, which results in a decrease in injected carrier density within the base region and thus an increase in the forward resistance of the device. A sensitivity range from 1010 nvt to > 1014 nvt is presently attainable. The accuracy of readout ranges from ± 50 per cent at 1010 nvt to ± 5 per cent at 1011 nvt and continues to improve at higher integrated fluxes. The effect of base width, forward current level, material properties, and processing parameters on the sensitivity and uniformity of device characteristics are discussed. The current-voltage behavior of the device is shown to correspond to a model by Rose(l) for diffusion-dominated double injection in semiconductors. The small size and ruggedness of the dosimeter and the simplicity of readout make it particularly suited for radiation-effects experimentation, accident dosimetry, and biological dosimetry.