Uniprocessor Systems Research Articles

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Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can significantly impact both power consumption and latency. Modern DRAM systems read data from cell arrays and populate a row buffer as large as 8 KB on a memory request. But only a small fraction of these bits are ever returned back to the CPU. This ends up wasting energy and time to read (and subsequently write back) bits which are used rarely. Traditionally, an open-page policy has been used for uni-processor systems and it has worked well because of spatial and temporal locality in the access stream. In future multi-core processors, the possibly independent access streams of each core are interleaved, thus destroying the available locality and significantly under-utilizing the contents of the row buffer. In this work, we attempt to improve row-buffer utilization for future multi-core systems. The schemes presented here are motivated by our observations that a large number of accesses within heavily accessed OS pages are to small, contiguous "chunks" of cache blocks. Thus, the co-location of chunks (from different OS pages) in a row-buffer will improve the overall utilization of the row buffer contents, and consequently reduce memory energy consumption and access time. Such co-location can be achieved in many ways, notably involving a reduction in OS page size and software or hardware assisted migration of data within DRAM. We explore these mechanisms and discuss the trade-offs involved along with energy and performance improvements from each scheme. On average, for applications with room for improvement, our best performing scheme increases performance by 9% (max. 18%) and reduces memory energy consumption by 15% (max. 70%).

Respec

Deterministic replay systems record and reproduce the execution of a hardware or software system. While it is well known how to replay uniprocessor systems, replaying shared memory multiprocessor systems at low overhead on commodity hardware is still an open problem. This paper presents Respec, a new way to support deterministic replay of shared memory multithreaded programs on commodity multiprocessor hardware. Respec targets online replay in which the recorded and replayed processes execute concurrently. Respec uses two strategies to reduce overhead while still ensuring correctness: speculative logging and externally deterministic replay. Speculative logging optimistically logs less information about shared memory dependencies than is needed to guarantee deterministic replay, then recovers and retries if the replayed process diverges from the recorded process. Externally deterministic replay relaxes the degree to which the two executions must match by requiring only their system output and final program states match. We show that the combination of these two techniques results in low recording and replay overhead for the common case of data-race-free execution intervals and still ensures correct replay for execution intervals that have data races. We modified the Linux kernel to implement our techniques. Our software system adds on average about 18% overhead to the execution time for recording and replaying programs with two threads and 55% overhead for programs with four threads.

Exact quantification of the sub-optimality of uniprocessor fixed priority pre-emptive scheduling

This paper examines the relative effectiveness of fixed priority pre-emptive scheduling in a uniprocessor system, compared to an optimal algorithm such as Earliest Deadline First (EDF).The quantitative metric used in this comparison is the processor speedup factor, equivalent to the factor by which processor speed needs to increase to ensure that any taskset that is schedulable according to an optimal scheduling algorithm can be scheduled using fixed priority pre-emptive scheduling, assuming an optimal priority assignment policy.For constrained-deadline tasksets where all task deadlines are less than or equal to their periods, the maximum value for the processor speedup factor is shown to be 1/Ω≈1.76322 (where Ω is the mathematical constant defined by the transcendental equation ln (1/Ω)=Ω, hence, Ω≈0.567143). Further, for implicit-deadline tasksets where all task deadlines are equal to their periods, the maximum value for the processor speedup factor is shown to be 1/ln (2)≈1.44270. The derivation of this latter result provides an alternative proof of the well-known Liu and Layland result.

An efficient response-time analysis for real-time transactions with fixed priority assignment

In the general context of tasks with offsets (general transactions), only exponential methods are known to calculate the exact worst-case response time (WCRT) of a task. The known pseudo-polynomial techniques give an upper bound of the WCRT. In this paper, we present a new worst-case response-time analysis technique (mixed method) for transactions scheduled by fixed priorities, and executing on a uniprocessor system. This new analysis technique gives a better (i.e. lower) pseudo-polynomial upper bound of the WCRT. The main idea is to combine the principle of exact calculation and the principle of approximation calculation, in order to decrease the pessimism of WCRT analysis, thus allowing improving the upper bound of the response time provided while preserving a pseudo-polynomial complexity. Then we define the Accumulative Monotonic property on which a necessary condition of feasibility is discussed. We also propose, to speed up the exact and mixed analysis, the dominated candidate task concept that allows reducing significantly the number of critical instants to study in an analysis.

SCHEDULING REAL-TIME TASKS IN MULTIPROCESSOR SYSTEMS USING GENETIC ALGORITHMS

Multiprocessors have been employed as a powerful computing means for executing real-time tasks, especially where a uniprocessor system would not be sufficient to execute all the tasks. This paper investigates dynamic scheduling algorithm for real-time tasks in a multiprocessor systems to obtain a feasible solution using genetic algorithms combined with earliest deadline first (EDF) and shortest computation time first (SCTF). A comparative study of the results obtained from simulations shows that genetic algorithm can be used to schedule tasks to meet their deadlines time , in addition to obtain high processor utilization.

Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures

Reduced energy consumption is one of the most important design goals for embedded application domains like wireless communication, multimedia and biomedical applications. The instruction memory hierarchy has been proven to be one of the most power hungry parts of the system. This paper introduces an architectural enhancement for the instruction memory to reduce energy consumption and improve performance. The proposed distributed instruction memory organization requires minimal hardware overhead and supports the execution of multiple incompatible loops in parallel in a uni-processor system. We present different methods to implement the loop controller architecture, compare them, and show that distributing the instruction memory helps to reduce the interconnect cost as well. This architecture enhancement can reduce the energy consumed in the instruction memory hierarchy by 59% and improve the performance by 22% compared to hardware based enhanced SMT based architectures.

Making secure processors OS- and performance-friendly

In today's digital world, computer security issues have become increasingly important. In particular, researchers have proposed designs for secure processors that utilize hardware-based memory encryption and integrity verification to protect the privacy and integrity of computation even from sophisticated physical attacks. However, currently proposed schemes remain hampered by problems that make them impractical for use in today's computer systems: lack of virtual memory and Inter-Process Communication support as well as excessive storage and performance overheads. In this article, we propose (1) address independent seed encryption (AISE), a counter-mode-based memory encryption scheme using a novel seed composition, and (2) bonsai Merkle trees (BMT), a novel Merkle tree-based memory integrity verification technique, to eliminate these system and performance issues associated with prior counter-mode memory encryption and Merkle tree integrity verification schemes. We present both a qualitative discussion and a quantitative analysis to illustrate the advantages of our techniques over previously proposed approaches in terms of complexity, feasibility, performance, and storage. Our results show that AISE+BMT reduces the overhead of prior memory encryption and integrity verification schemes from 12% to 2% on average for single-threaded benchmarks on uniprocessor systems, and from 15% to 4% for coscheduled benchmarks on multicore systems while eliminating critical system-level problems.

Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis

To achieve an automated implementation for the application-specific heterogeneous multiprocessor systems-on-chip (MPSoC), partitioning and mapping the sequential programs onto multiple parallel processors is one of the most difficult challenges. However, the existing traditional parallelizing techniques cannot solve the MPSoC-related problems effectively, so designers are still required to manually extract the concurrency potentials in the program. To solve this bottleneck, an automated application partition technique is needed. However, completely automatic parallelism is ineffective, so it is promising to explore concurrency for certain practical special structures. To settle those issues, this paper proposes a template-based algorithm to automatically partition a special load-compute-store (LCS) loop structure. Since specific-instruction customization for the application specific instruction-set processors (ASIPs) has interactions with task partitioning, the proposed algorithm integrates the dynamic pipelining and ASIP techniques using an iterative improvement strategy: first, an initial pipelining scheme is generated to obtain the maximum parallelism; second, under the primary partition results specific instructions are customized respectively for each subprogram; third, the program is repartitioned via pipelining under the specific instruction configurations. The proposed method has been implemented in the context of a commercial extensible multiprocessor design flow, using the Xtensa-based XTMP platform from Tensilica Inc. Based on a case study of Fast Fourier Transform (FFT), the experimental results indicate that the partitioned programs by the proposed method demonstrate an average speedup of 10× compared to the original sequential programs which have not been partitioned and run on the uniprocessor system.

Reconstruction for Time-Domain In Vivo EPR 3D Multigradient Oximetric Imaging—A Parallel Processing Perspective

Three-dimensional Oximetric Electron Paramagnetic Resonance Imaging using the Single Point Imaging modality generates unpaired spin density and oxygen images that can readily distinguish between normal and tumor tissues in small animals. It is also possible with fast imaging to track the changes in tissue oxygenation in response to the oxygen content in the breathing air. However, this involves dealing with gigabytes of data for each 3D oximetric imaging experiment involving digital band pass filtering and background noise subtraction, followed by 3D Fourier reconstruction. This process is rather slow in a conventional uniprocessor system. This paper presents a parallelization framework using OpenMP runtime support and parallel MATLAB to execute such computationally intensive programs. The Intel compiler is used to develop a parallel C++ code based on OpenMP. The code is executed on four Dual-Core AMD Opteron shared memory processors, to reduce the computational burden of the filtration task significantly. The results show that the parallel code for filtration has achieved a speed up factor of 46.66 as against the equivalent serial MATLAB code. In addition, a parallel MATLAB code has been developed to perform 3D Fourier reconstruction. Speedup factors of 4.57 and 4.25 have been achieved during the reconstruction process and oximetry computation, for a data set with 23 × 23 × 23 gradient steps. The execution time has been computed for both the serial and parallel implementations using different dimensions of the data and presented for comparison. The reported system has been designed to be easily accessible even from low-cost personal computers through local internet (NIHnet). The experimental results demonstrate that the parallel computing provides a source of high computational power to obtain biophysical parameters from 3D EPR oximetric imaging, almost in real-time.

Multi-processor programming in the embedded system curriculum

Teaching embedded system design is challenging, as the subject covers a wide range of aspects, and also involves skills that students do not learn from a text book. As a result, hands-on projects, with varying degree of complexity, are the most common approach in existing courses. Traditionally, the projects are limited to uni-processor systems, and do not address the complications involved in parallelising applications and mapping them to multi-processor systems. In this paper, we describe a two-year-old embedded systems design course given at Eindhoven University of Technology. In the course, groups of four students are faced with the problem of putting an embedded JPEG decoder on the market within one semester. The starting point is a decoder written in sequential C and an embedded multiprocessor system, running on an FPGA. We describe the ideas and organisation of the course, and give examples of what challenges the students, as well as the instructors, are faced with. We exemplify results and give suggestions to those wishing to teach embedded multi-processor programming elsewhere.

Etat de l'art sur la robustesse temporelle des systèmes temps-réel monoprocesseur

In this paper we propose a state of the art on the temporal robustness of uniprocessor real-time systems. The task model is the classical periodic task model defined by a Worst Case Execution Time (WCET), a Period and a late termination Deadline. We consider Fixed Priority highest priority first (FP) and Earliest Deadline First (EDF) scheduling policies. The temporal robustness studies how to adapt theoretical feasibility conditions, to take into account possible deviations on the WCETs, periods or deadlines of the tasks. Sensitivity analysis aims at defining in the dimensioning phase the maximum acceptable deviations from the task parameters. We then focus on existing solutions to handle those variations at run time.

M-CASH: A real-time resource reclaiming algorithm for multiprocessor platforms

Resource reclaiming schemes are typically applied in reservation-based real-time uniprocessor systems to support efficient reclaiming and sharing of computational resources left unused by early completing tasks, improving the response times of aperiodic and soft tasks in the presence of overruns. In this paper, we introduce a novel and efficient reclaiming algorithm, named M-CASH, for multiprocessor platforms. M-CASH leverages the resource reservation approach offered by the Multiprocessor CBS server offering significant improvements. The correctness of the algorithm is formally proven and its performance is evaluated through extensive synthetic simulations.

A BASELINE MODEL FOR SCHEDULING SOFT REAL TIME TASKS ON UNI-PROCESSOR SYSTEMS

In this paper, we consider the different performance parameters that influence the scheduling of soft real time tasks on uni-processor systems. This environment is rich of parameters that affect the rejection ratio of the system. This work models such stochastic environment and proposes a baseline model that estimates the rejection ratio of the system before applying any special scheduling algorithm. The model presents many cases where the system produces a small rejection ratio without the need for any special scheduling algorithm. We validate our analytical model with simulations that represent the real computing environment. The results of our simulations show that our mathematical model can predict the expected percentage of tasks that miss their deadline accurately.

Soft Real-Time Fuzzy Task Scheduling for Multiprocessor Systems

All practical real-time scheduling algorithms in multiprocessor systems present a trade-off between their computational complexity and performance. In real-time systems, tasks have to be performed correctly and timely. Finding minimal schedule in multiprocessor systems with real-time constraints is shown to be NP-hard. Although some optimal algorithms have been employed in uni-processor systems, they fail when they are applied in multiprocessor systems. The practical scheduling algorithms in real-time systems have not deterministic response time. Deterministic timing behavior is an important parameter for system robustness analysis. The intrinsic uncertainty in dynamic real-time systems increases the difficulties of scheduling problem. To alleviate these difficulties, we have proposed a fuzzy scheduling approach to arrange real-time periodic and non-periodic tasks in multiprocessor systems. Static and dynamic optimal scheduling algorithms fail with non-critical overload. In contrast, our approach balances task loads of the processors successfully while consider starvation prevention and fairness which cause higher priority tasks have higher running probability. A simulation is conducted to evaluate the performance of the proposed approach. Experimental results have shown that the proposed fuzzy scheduler creates feasible schedules for homogeneous and heterogeneous tasks. It also and considers tasks priorities which cause higher system utilization and lowers deadline miss time. According to the results, it performs very close to optimal schedule of uni-processor systems.

The impact of wrong-path memory references in cache-coherent multiprocessor systems

The core of current-generation high-performance multiprocessor systems is out-of-order execution processors with aggressive branch prediction. Despite their relatively high branch prediction accuracy, these processors still execute many memory instructions down mispredicted paths. Previous work that focused on uniprocessors showed that these wrong-path (WP) memory references may pollute the caches and increase the amount of cache and memory traffic. On the positive side, however, they may prefetch data into the caches for memory references on the correct-path. While computer architects have thoroughly studied the impact of WP effects in uniprocessor systems, there is no comparable work for multiprocessor systems. In this paper, we explore the effects of WP memory references on the memory system behavior of shared-memory multiprocessor (SMP) systems for both broadcast and directory-based cache coherence. Our results show that these WP memory references can increase the amount of cache-to-cache transfers by 32%, invalidations by 8% and 20% for broadcast and directory-based SMPs, respectively, and the number of writebacks by up to 67% for both systems. In addition to the extra coherence traffic, WP memory references also increase the number of cache line state transitions by 21% and 32% for broadcast and directory-based SMPs, respectively. In order to reduce the performance impact of these WP memory references, we introduce two simple mechanisms—filtering WP blocks that are not likely-to-be-used and WP aware cache replacement—that yield speedups of up to 37%.

R-Kleene: A High-Performance Divide-and-Conquer Algorithm for the All-Pair Shortest Path for Densely Connected Networks

We propose a novel divide-and-conquer algorithm for the solution of the all-pair shortest-path problem for directed and dense graphs with no negative cycles. We propose R-Kleene, a compact and in-place recursive algorithm inspired by Kleene's algorithm. R-Kleene delivers a better performance than previous algorithms for randomly generated graphs represented by highly dense adjacency matrices, in which the matrix components can have any integer value. We show that R-Kleene, unchanged and without any machine tuning, yields consistently between 1/7 and 1/2 of the peak performance running on five very different uniprocessor systems.

Application of Thread-Level Parallel Programming to Thermohydrodynamic Lubrication Computation

This study presents a performance evaluation of a portable parallel programming paradigm, the OpenMP, for thermohydrodynamic (THD) lubrication analysis. The THD model is described by two coupled partial differential equations, a simplified generalized Reynolds equation and a 3-D time-dependent energy equation. The numerical methods used for solving these equations are coded and compiled as a multithread application to minimize execution time in a dual-CPU workstation. It was found that the program coded in thread-level parallelism can effectively use the computing resources in the current setup. The attributes of conditional compilation and incremental parallelization of OpenMP make it a powerful tool for fine-grain applications in shared-memory platforms. A program coded in thread-level parallelism should understand the caching operation to fully exploit the capacity of coming dual- or multi-core desktop CPUs in either uniprocessor or multiprocessor systems. As illustrated in this study, some of the parallel programming techniques used in solving the Reynolds equation and the thermal energy equation can facilitate applications using similar lubrication models. Presented at the STLE Annual Meeting in Calgary, Alberta, Canada May 7–11, 2006 Review led by Gita Talmage

Efficient address remapping in distributed shared-memory systems

As processor performance continues to improve at a rate much higher than DRAM and network performance, we are approaching a time when large-scale distributed shared memory systems will have remote memory latencies measured in tens of thousands of processor cycles. The Impulse memory system architecture adds an optional level of address indirection at the memory controller. Applications can use this level of indirection to control how data is accessed and cached and thereby improve cache and bus utilization and reduce the number of memory accesses required. Previous Impulse work focuses on uniprocessor systems and relies on software to flush processor caches when necessary to ensure data coherence. In this paper, we investigate an extension of Impulse to multiprocessor systems that extends the coherence protocol to maintain data coherence without requiring software-directed cache flushing. Specifically, the multiprocessor Impulse controller can gather/scatter data across the network while its coherence protocol guarantees that each gather request gets coherent data and each scatter request updates every coherent replica in the system. Our simulation results demonstrate that the proposed system can significantly outperform conventional systems, achieving an average speedup of 9X on four memory-bound benchmarks on a 32-processor system.

A performance study of normalized explicit finite element approximate inverse preconditioning on uniprocessor and multicomputer systems

PurposeTo propose novel parallel/distributed normalized explicit finite element (FE) approximate inverse preconditioning for solving sparse FE linear systems.Design/methodology/approachThe design of suitable methods was the main objective for which several families of the normalized approximate inverse, based on sparse normalized approximate factorization, are produced. The main motive for the derivation of the new normalized approximate inverse FE matrix algorithmic techniques is that they can be efficiently used in conjunction with normalized explicit preconditioned conjugate gradient (NEPCG) – type schemes on parallel and distributed systems. Theoretical estimates on the rate of convergence and computational complexity of the NEPCG method are also derived.FindingsApplication of the proposed method on a three‐dimensional boundary value problem is discussed and numerical results for uniprocessor systems along with speed‐ups and efficiency for multicomputer systems are given. These results tend to become optimum, which are in qualitative agreement with the theoretical results presented for uniprocessor and distributed memory systems, using message passing interface (MPI) communication library.Research limitations/implicationsFurther parallel algorithmic techniques will be investigated in order to improve the speed‐ups and the computational complexity of the parallel normalized explicit approximate inverse preconditioning.Originality/valueThe proposed parallel/distributed normalized explicit approximate inverse preconditioning, using approximate factorization and approximate inverse algorithms, is an efficient computational method that is valuable for computer scientists and for scientists and engineers in engineering computations.

X10

It is now well established that the device scaling predicted by Moore's Law is no longer a viable option for increasing the clock frequency of future uniprocessor systems at the rate that had been sustained during the last two decades. As a result, future systems are rapidly moving from uniprocessor to multiprocessor configurations, so as to use parallelism instead of frequency scaling as the foundation for increased compute capacity. The dominant emerging multiprocessor structure for the future is a Non-Uniform Cluster Computing (NUCC) system with nodes that are built out of multi-core SMP chips with non-uniform memory hierarchies, and interconnected in horizontally scalable cluster configurations such as blade servers. Unlike previous generations of hardware evolution, this shift will have a major impact on existing software. Current OO language facilities for concurrent and distributed programming are inadequate for addressing the needs of NUCC systems because they do not support the notions of non-uniform data access within a node, or of tight coupling of distributed nodes.We have designed a modern object-oriented programming language, X10, for high performance, high productivity programming of NUCC systems. A member of the partitioned global address space family of languages, X10 highlights the explicit reification of locality in the form of places }; lightweight activities embodied in async , future , foreach , and ateach constructs; a construct for termination detection ( finish ); the use of lock-free synchronization ( atomic blocks ); and the manipulation of cluster-wide global data structures. We present an overview of the X10 programming model and language, experience with our reference implementation, and results from some initial productivity comparisons between the X10 and Java™ languages.