Undoped SiGe Research Articles

Realization of High-Hole Mobility and Low-Hole Concentration in Polycrystalline Ge Layers By Hydrogen Passivation

IntroductionPolycrystalline Ge thin films are highly promising for next-generation semiconductor devices, such as thin film transistors and solar cells. To optimize their grain size and mobility, we meticulously controlled the density of amorphous Ge, a key precursor for solid-phase growth, by adjusting the deposition temperature (T d)[1,2]. Despite these advances, the synthesized films still exhibit high concentrations of defect-induced acceptors (hole concentration p > 1017 cm−3), presenting significant challenges in Fermi level control, crucial for device applications. In this study, we aimed to synthesize low-defect polycrystalline Ge thin films through hydrogen passivation of solid-phase crystallized Ge. We achieved a significant reduction in p while maintaining high mobility, utilizing hydrogen plasma treatment on large-grain polycrystalline Ge films under optimized conditions. Experimental ProceduresGe was deposited onto quartz glass substrates to form 100 nm thick amorphous Ge films. These were annealed at 450 ℃ in a nitrogen atmosphere for solid-phase crystallization. Afterward, the polycrystalline Ge films underwent hydrogen plasma treatment at different powers (W P = 150, 300, 450 W) to facilitate hydrogen diffusion. Vacuum post-annealing (PA) was then performed to further enhance hydrogen activation. Results and DiscussionWe examined how hydrogen plasma irradiation time (t H) affects the electrical properties of samples deposited at room (T d = 50 ℃) and elevated temperatures (T d = 125 ℃) for each W P setting. Figures 1(a) and (b) show that the Ge layer's grain size after annealing varies significantly with T d; the T d = 125 ℃ sample had a grain size over an order of magnitude larger than the T d = 50 ℃ sample. Figures 1(c) and (d) reveal the plasma treatment's impact on electrical properties: hydrogen introduction decreased p under both conditions. The T d = 50 ℃ samples saw a reduction in p to 5.0 × 1017 cm−3, while the T d = 125 ℃ samples progressively lowered p with t H to a minimum of 1.2 × 1015 cm−3. These findings highlight a limit to defect compensation through plasma treatment and emphasize the crucial role of initial Ge film quality in achieving low p-values. Furthermore, an increase in W P correlated with a reduction in p, likely due to deeper hydrogen penetration into the Ge matrix. Additionally, μ was impacted differently in each scenario: in the T d = 50 ℃ sample, μ decreased due to hydrogen passivation. In contrast, for the T d = 125 ℃ samples, μ initially decreased following plasma irradiation but subsequently increased with extended t H. Notably, a plasma treatment at W P = 300 W for 20 minutes achieved a balance, maintaining high μ (155 cm² V−1 s−1) while also achieving a low p (2.3 × 1015 cm−3).We also applied low-temperature PA to samples that had undergone hydrogen plasma treatment. Figure 2(a) reveals that PA at 200 ℃ resulted in further reductions in p and significant enhancements in μ. Conversely, PA at 300 ℃ reversed the improvements, aligning p and μ values with those seen prior to plasma treatment. These observations suggest that PA at appropriate temperatures promotes the passivation of acceptor defects and grain boundary trapping, whereas higher PA temperatures facilitate hydrogen desorption from Ge.We standardized the PA temperature at 200 ℃ and varied t PA (Figure 2(b)). An increase in t PA initially led to a decrease in p, which then began to rise, while μ initially rose and subsequently fell. This dynamic suggests an equilibrium between the effects of defect passivation and hydrogen desorption. For a t PA of 4 hours, we achieved optimal properties with a low p (4 × 1014 cm−3) and high μ (370 cm² V−1 s−1), indicating an effective balance between these critical parameters. ConclusionFigure 3 presents a comparative analysis of the electrical properties of undoped polycrystalline Ge, GeSn, and SiGe thin films, each less than 150 nm in thickness, grown on insulating substrates utilizing various deposition techniques. Universally, polycrystalline Ge layers demonstrate p exceeding 1017 cm−3 across all applied methods, attributable to intrinsic acceptor defects. Adding minor Sn concentrations to Ge modestly improves characteristics, reducing p and enhancing μ. Meanwhile, increasing Si in SiGe films—especially over 50%—substantially lowers p but significantly diminishes μ due to increased carrier effective mass and grain boundary barriers. Remarkably, the polycrystalline Ge layers developed in this study not only exhibited the lowest p observed in polycrystalline Ge-based thin films but also maintained enhanced μ. This constitutes a significant advancement, considerably enhancing the electrical properties traditionally associated with conventional Ge thin films and represents a pivotal development in semiconductor material engineering. Figure 1

Effects of Ge and B Concentration in Selective Epitaxial Growth of Si1-XGex(:B) at Low-Temperature

As two-dimensional devices approach their scaling limits, monolithic complementary field-effect transistors have emerged to meet the demands of advanced transistors. A low thermal budget process is essential to prevent damage to the underlying layers while forming upper layers. Therefore, a low-temperature approach for the selective epitaxial growth (SEG) of SiGe(:B) in source-drain formation is necessary. The cyclic deposition and etch method was employed for its high selectivity, highlighting the need for further research into the incubation characteristics of B-doped SiGe. [1] We investigated the incubation behavior of SiGe(:B) on SiO2 under varying Ge and B concentrations in an ultra-high vacuum-chemical vapor deposition (UHV-CVD) chamber. In this study, we investigated the influence of the Ge and B concentrations on the incubation time for SiGe(:B) on SiO2, comparing it with the epitaxial growth on Si(100) and Si(111). First, we analyzed the incubation properties of undoped Si1-xGex (0 < x < 0.4) layers. We then explored the effect of B concentration by varying the B flow rate. Our findings indicate the higher Ge concentrations extend the incubation time, independent of the total gas flow rate. In contrast, B doping reduces the incubation time compared to with that of undoped SiGe, and increasing B concentration further shortens the incubation time. Atomic force microscopy and scanning electron microscopy were used to examine amorphous formation on SiO2. In addition, high-resolution X-ray diffractometry and ellipsometry were used to analyze Ge and B concentrations, as well as growth thickness. Our study offers comprehensive insights into the low- temperature SEG process window for SiGe(:B). Acknowledgment This work was supported by the Technology Innovation Programs (RS-2023-00235609) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).

Low-temperature epitaxial SiGe:P for gate-all-around n-channel metal-oxide-semiconductor devices

This study investigates the viability of Si1−x Ge x :P (x ≤ 0.3) as a novel source/drain material for n-channel Metal-Oxide-Semiconductor for Gate-All-Around (GAA) transistors, addressing the challenges posed by the evolving semiconductor technology. Utilizing a reduced-pressure chemical vapor deposition system, undoped SiGe with low Ge contents were grown at temperatures of ≤500 °C. The addition and optimization of phosphorous doping using phosphine results in improved surface morphology and increased active carrier concentration. The study compares Si1−x Ge x :P with different silicon precursors and temperatures, emphasizing the potential for maintaining high growth rates at lower temperatures when using Si3H8. Ti/Si1−x Ge x :P stacks reveal a promising reduction in contact resistivity with decreasing the Ge content, particularly when incorporating thin Si:P cap layers at the Ti/Si1−x Ge x :P interface. This comprehensive study highlights the potential of Si1−x Ge x :P as an alternative material for advanced GAA transistor technologies, offering improved mobility and meeting the thermal budget requirements.

Impact of Nanosecond Laser Annealing on the Electrical Properties of Highly Boron-Doped Ultrathin Strained Si0.7Ge0.3 Layers

The CMOS scaling beyond 10 nm technology node requires high active dopant concentrations in source/drain modules to minimize contact resistance. Pulsed laser annealing has been targeted by chip manufacturers as a future option to enhance the activation level inside highly doped SiGe:B and Si:P regions, mostly used in PMOS and NMOS transistor fabrication, respectively. Indeed, this annealing process allows reaching high temperatures (above melt threshold), locally (~100nm below the surface) and with extremely fast temperature ramp rates (>109 °C/s), so that high doping levels have been demonstrated both in pure Si and Ge [1]. In a recent study, structural investigations allowed identifying the best conditions to obtain fully strained and defect-free undoped SiGe layers by liquid phase epitaxial regrowth (LPER) [2]. In this work, we report an analysis on the activation of boron dopants in similar layers. In-situ boron-doped 30 nm thick pseudomorphic Si0.7Ge0.3 layers were grown on p-type bulk Si (100) by CVD. Three different boron concentrations were incorporated inside these layers: 7.8x1019 (A), 1.4x1020 (B) and 2.3x1020 cm-3 (C). By combining the boron chemical profiles with the corresponding Hall effect measurements (Hall scattering factor: 0.35), it was possible to estimate the activation rate inside the as-grown strained SiGe layers and the impact of the possible inactive dopants on the transport properties. From the lowest to the highest boron chemical concentration, we found activation rates of ~100%, ~80% and ~60%, with no significant carrier mobility degradation, even in the sample with the highest fraction of inactive dopants.The SiGe layers were subsequently laser annealed in a SCREEN-LT3100 platform operating at 308 nm (XeCl laser) with a pulse duration around 160 ns. The laser energy densities (ED) ranged from 1.20 to 2.40 J/cm2 in order to investigate all the various annealing regimes. Results obtained using several characterization techniques were combined to determine the laser annealing regimes, quantify surface roughness and assess the layers’ composition, strain and crystalline quality. These results were compared to electrical measurements performed to analyse the evolution of the electrical parameters as a function of the laser anneal conditions, particularly the activation rate.For the lowly-doped and fully activated layer (A), the sheet resistance increases rapidly at the melt threshold (1.5 J/cm2, cf. Fig. 1, red curve), concomitantly with the appearance of a partial relaxation inside the layer (Fig. 2) and the formation of extended defects. The defects may induce a local dopant deactivation, while strain relaxation can result in a modification of the transport properties of the material (modified Hall scattering factor). Both phenomena can be therefore responsible for the observed increase of the sheet resistance. In contrast, for laser EDs allowing complete melt of the layer (i.e. beyond 2.0 J/cm2), the sheet resistance decreases with increasing ED and full activation is achieved (Fig. 3, red curve) together with strain recovery (Fig. 2) and no observable defects.For the highly-doped and partially activated layer (C), partial relaxation also occurs at the melt threshold (Fig. 2). However, thanks to the strain compensation effect of the small boron atoms, the relaxation level is lower compared to the lowly-doped sample and more quickly recovered when increasing the ED (no defects observed at 1.95 J/cm2, Fig. 4). In addition, the sheet resistance is found to continuously decrease as a function of the ED (Fig. 1, blue curve) independently of the strain state of the structure. This suggests that, in addition to the previously described phenomena, the initially inactive dopants are progressively incorporated into substitutional positions by LPER. Indeed, when full melt and strain recovery is achieved, a 100% dopant activation is also observed (Fig. 3, blue curve). Characterizations made on sample B suggest a similar behaviour to that of sample C.Finally, further results will be reported from additional experiments aiming at (i) better understanding the impact of strain relaxation on dopant activation and (ii) optimizing the laser annealing process to avoid relaxation. These experiments include the use of a shorter laser pulse for the annealing of the strained SiGe layers, as well as the comparison with results obtained from fully-relaxed boron-doped SiGe annealed under similar laser conditions.Acknowledgements:This work was supported by the European Union’s Horizon 2020 research and innovation program under grant agreement No. 871813 MUNDFAB.

B and Ga Co-Doping in Epitaxial SiGe: Challenges and Opportunities

Contact resistances are inherent to any device connected to the outside world. Lowering their contribution is essential for high-performance applications. This is the case for advanced Si CMOS technologies, for which series resistance parasitics become the main performance detractor from the 14 nm node onwards [1-2]. For p-type fin and gate-all-around field effect transistors, focus is placed on Ti contacts to p-Si1-xGex source/drain (S/D) [3].Several non-equilibrium doping techniques have been explored to enhance active doping in S/D regions and decrease contact resistivities (ρc) down to ≤ 1x10-9 Ω.cm2. In most cases, low temperature doping processes are used to favor the incorporation of dopants and their activation [4]. Alternative dopants, with higher solid solubilities and advantageous segregation behaviors favoring the formation of dopant-enriched films at the metal-semiconductor interface, are also evaluated. Very low ρc values have e.g. been reported by combining Ga ion implantation in Si0.4Ge0.6 and ns laser annealing [5]; whereas in situ doping was optimized in Si1-xGex:B [6-9] and Si0.5Ge0.5:B:Ga, grown by chemical vapor deposition using metalorganic (MO) Ga precursors [4,10]. In this contribution, we highlight opportunities and challenges offered by this approach.The maximum solubility of Ga in Ge is more than 100x higher than that of B [11-12]. However, controlling the incorporation and distribution of Ga dopants in Si0.5Ge0.5(:B) is not straightforward. This relates to the tendency for Ga to segregate towards the surface, as reported in [4,10] and shown in Fig. 1(a). We rely on Si0.5Ge0.5:B:Ga co-doped epi layers in which bulk resistivity is lowered thanks to high B-doping concentrations, while contact resistivity minimization is expected from Ga segregation towards the contact region. It appears, however, that Ga surface doping concentrations significantly higher than 3E20 cm-3 are required to efficiently reduce ρc [5,13]. Targeting such high surface concentrations comes with the risk of Ga agglomeration into Ga-rich defects on S/D surfaces. Another detractor lies in the possible consumption of superficial Ga during native oxide removal preceding contact processing. Results presented in Fig. 1(b) suggest such a ~ 10x decrease in Ga concentration close to the S/D surface after native oxide removal. Systematic investigations are underway to clarify this aspect, which could lead us to reconsider our contacting scheme.Activating high levels of Ga dopants in in situ doped epi layers is an additional challenge. Preliminary results indicate that, in the conditions explored in this work, only a small fraction of the dopants incorporated in SiGe:Ga are active. This limitation may be attributed to Ga dopants clustering or to interactions with unwanted C incorporated during growth. Fig. 1(c) illustrates our effort in reducing C incorporation in SiGe:B:Ga by utilizing 2 different Ga MO precursors, namely MO1 and MO2, while keeping all other growth parameters the same. For this test, an undoped SiGe cap was used to separate contributions from adventitious C and C really incorporated in the SiGe:B:Ga layer. Ga profiles appear to be affected by the capping, with part of the Ga dopants migrating towards the top part of the stack. C impurities are on the other hand assumed to be frozen in their original position [14]. While the level of incorporated C is not significantly affected by the choice of precursor, a shorter Ga incorporation delay, materialized by blue arrows in Fig. 1(c), and a larger [Ga] / [C] ratio are extracted from the layer grown with MO2.

Thermal expansion of bulk nanostructured n-type SiGe nanocomposite from 300 to 1400 K

The use of the nanostructured nanocomposites aims to improve the peak figure of merit (ZT) values of thermoelectric alloys. In addition to ZT, the coefficients of the thermal linear expansion (CTLE) of these alloys are equally important for estimating stresses imposed by the thermal cycling inherent to waste heat recovery operations. In this study, we report the calculated “technical alpha”, i.e., the experimental mean CTLE values for the bulk nanostructured n-type Si80Ge20 alloy doped with phosphorus at 298–1220 K. The elemental composition of the spark plasma sintered (SPS)-specimen after thermal cycling in the infrared furnace is characterized by means of AES spectroscopy in combination with ion sputtering. Small amounts of contaminants, such as Fe and O, and large losses of P are detected. Elongations have been measured using ULVAC DL-1500-RH high-speed dilatometer with various rates of heating and cooling. Anomalous thermal behavior of the n-type Si80Ge20(P2.2) composite is observed at high temperatures. Previously, the same anomaly was detected in the temperature dependence of the elongation of pure silicon. There are some discrepancies between our measurements of the thermal expansion of nanostructured n-SiGe composites and those reported in the literature. Moreover, in this study, SiGe solid solution is also studied to verify the additive scheme and to explore deviations from it for predicting CTLE values at higher temperature on the basis of the properties of the pure components. These calculations of the CTLE of undoped SiGe alloys match with the results of the dilatometric and X-ray experiments conducted during the period 1964–1987 and the calculations based on other theoretical approaches.

(Invited) A Brief History of Selective Epitaxy (at IBM SRDC)

Over more than a decade—and half a dozen technology nodes—selective expitaxy has consistently been a major performance element, propelling logic devices to their ultimate targets. Throughout this period (the “Epi Renaissance”), a huge variety of epitaxial processes have been evaluated across the semiconductor industry. Because each technology generation has unique constraints and process assumptions, these epitaxy processes have varied significantly in shape, size, and composition. And of course not all survived to be implemented in full production. This presentation gives a retrospective survey of each of these epitaxial processes, ranging from a simple, single undoped Si raised source/drain to multi-pass growth with complex multi-layer film stack. Selective epitaxy at IBM SRDC began with an undoped selective Si raised source drain (RSD) at the 90nm technology node, used to improve the silicide formation and placement. This was a key enabling feature of the Si on SiGe on insulator (SGOI) technology [1]. Since the silicide had difficulties with the SiGe underlayer, a selective epitaxial Si solution allowed significantly improved contact resistance. SGOI showed great promise on long channel devices, and due to the uniaxial nature of the strain it showed a clear performance benefit on both NFET and PFET. Unfortunately, the short channel devices were consistently degraded, so for the ultimate performance targets IBM instead turned to stressed nitride liners to deliver channel strain [2], while Intel introduced embedded SiGe source/drain (eSiGe) [3]. IBM incorporated eSiGe as a PFET performance element starting at the 65 nm node. However, instead of an in-situ boron doped eSiGe grown just prior to silicide (late eSiGe) similar to what Intel had published, IBM used a lower %Ge, undoped SiGe film grown just after gate module (early eSiGe). Early eSiGe was effectively a “drop-in” solution that allowed for minimal disruption to the existing integration and device design while still providing significant performance gains via channel strain [4]. For the 45nm node IBM published a novel method called Hybrid Orientation Substrate (HOT) that enabled PFET performance gain by changing the PFET Si crystal orientation from <100> to <110>. This method utilized a SOI wafer with <100> top Si layer bonded to a <110> handle wafer. At the beginning of the process, the PFET regions were etched down through the buried oxide, and a thick, undoped selective Si epi was then re-grown on the <110> substrate. In contrast to SGOI the benefit of HOT was demonstrated even on short channel devices. Even better, this mobility increase was shown to be additive with eSiGe strain [5]. Unfortunately a combination of factors including significantly higher substrate cost, area density penalty from expanded groundrules, and concerns about defectivity of the selective epitaxial re-growth prevented it from being implemented in full manufacturing. Instead of HOT, a second generation early eSiGe process was developed with closer proximity to the gate, and increased recess depth [6]. At the 32nm node IBM was focused on the switch to high-K with metal gate, and again IBM and Intel’s solutions diverged. IBM and partner companies used a “gate first” integration flow, contrasted with Intel’s “gate last” replacement metal gate process. Since differential metal workfunction tuning was unavailable in the gate-first integration, IBM introduced a second epitaxy step, growing a thin layer of channel SiGe on the PFET in order to separately tune the PFET threshold voltage [7], and increase performance [8]. Despite remaining planar and gate first, 22nm saw multiple disruptive changes in the source/drain epi module. IBM gained an industry first with the introduction of strained Si:CP in the NFET S/D, a process that required cyclic dep/etch in order to achieve high substitutional carbon incorporation [9]. On the PFET side, the reduced dimensions and the effect of ion implant lateral straggle finally forced a switch from early to late eSiGe. This change drove increased complexity in the epi by adding a buffer layer to control dopant out-diffusion, a ramped high-boron main layer, and a cap layer for improved silicide. Additionally, both NFET and PFET benefited from the introduction of an integrated preclean module, where the wafer does not break vacuum in between oxide etch and epitaxial growth. Today, the 14nm node marks the arrival of FinFETs at the SRDC – with significant integration differences compared to Intel’s FinFET solution. IBM chose to stay with SOI substrate, leading to challenges with the source/drain recess for embedded SiGe. Eventually, IBM sidestepped the recess issue by implementing cladded epitaxy for both the PFET and NFET source/drain, focusing on improving performance by lowering contact resistance instead of straining the channel [10]. Figure 1

Undoped accumulation-mode Si/SiGe quantum dots

We report on a quantum dot device design that combines the low disorder properties of undoped SiGe heterostructure materials with an overlapping gate stack in which each electrostatic gate has a dominant and unique function—control of individual quantum dot occupancies and of lateral tunneling into and between dots. Control of the tunneling rate between a dot and an electron bath is demonstrated over more than nine orders of magnitude and independently confirmed by direct measurement within the bandwidth of our amplifiers. The inter-dot tunnel coupling at the charge configuration anti-crossing is directly measured to quantify the control of a single inter-dot tunnel barrier gate. A simple exponential dependence is sufficient to describe each of these tunneling processes as a function of the controlling gate voltage.

Silicon germanium interdiffusion in SiGe device fabrication: A calibrated TCAD model

SiGe alloys are used in many types of electronic devices. For upcoming FinFET technologies, there is interest in the use of SiGe heterostructures in the complete mole fraction range (0–100% Ge atoms). For high Ge mole fraction and small device dimensions, interdiffusion of Si and Ge atoms can lead to critical changes in the distribution of Si and Ge atoms, impacting channel strain and carrier mobility. A process model for Si–Ge interdiffusion has been developed which covers the needs for actual device fabrication processes. Interdiffusion is understood to be correlated with the diffusion of vacancies, self-interstitials, and dopant-defect pairs. We consider the impact of non-equilibrium point defect concentrations (such as interstitial super-saturation after ion implantation), the impact of compressive or tensile strain, and a twofold impact of doping: first, doping determines the local electron concentration and thereby the abundance of charged point defects, and second, the diffusion of dopant-defect pairs can contribute to the interdiffusion of Si and Ge atoms. The model covers the full range of possible Ge mole fractions (0–100%). For undoped SiGe, it has been calibrated against a broad range of published experimental data for radio-tracer diffusion in SiGe and for interdiffusion in biaxially strained SiGe heterostructures grown on Si, stress-relaxed SiGe, or Ge. The extensions for doped SiGe are presented with a reference to few interdiffusion data for heavily doped SiGe heterostructures. Finally, the model has been consistently integrated into a set of models for the continuum process simulation of point defects and dopants in pure Si, SiGe, and pure Ge, in Sentaurus Process.

Dielectric function of Si1−xGex films grown on silicon-on-insulator substrates

The dielectric functions of undoped and P-doped Si1−xGex (SiGe) films with a compressive strain on silicon-on-insulator (SOI) substrates are obtained by using spectroscopic ellipsometry. The respective Kato–Adachi and Tauc–Lorentz models are best fitted to the undoped and P-doped SiGe films to obtain their complex dielectric functions. The undoped SiGe films are characterized by multimodal peaks in the dielectric function, whereas the P-doped SiGe films exhibit only a broad peak. Further, the E0 and E1 critical points (CPs) of the undoped SiGe films are strongly dependent on the Ge concentration, whereas the E2 CPs are independent of concentration. The E0 and E2 CPs in the undoped SiGe films on an SOI substrate are lower than those of SiGe on a bulk-Si substrate owing to the higher strain. For P doping in SiGe, its dose causes non-monotonic variations in Eg and E0.

Rapid Epitaxial Growth of Si and SiGe Mono-Crystalline Films on Silicon-on-Glass Substrates by Reactive CVD Using SiH4, GeH4, and F2

ABSTRACTWe have succeeded in the rapid epitaxial growth of Si, Ge, and SiGe films on Si substrates below 670 ºC by reactive CVD utilizing the spontaneous exothermic reaction between SiH4, GeH4, and F2. Mono-crystalline SiGe epitaxial films with Ge composition ranging from 0.1 to 1.0 have been successfully grown by reactive CVD for the first time.This technique has also been successfully applied to the growth of these films on silicon-on-glass substrates by a 20 - 50 ºC increase of the heating temperature. Over 10 μm thick epitaxial films at 3 nm/s growth rate are obtained. The etch pit density of the 5.2 μm-thick Si0.5Ge0.5 film is as low as 5 x 106 cm-2 on top. Mobilities of the undoped SiGe and Si films are 180 to 550 cm2/Vs, confirming the good crystallinity of the epitaxial films.

Numerical approach to resolve mass interference in depth profiling As in SiGe

AbstractSIMS analysis of SiGe material is intricate and challenging due to the mass interference effects. For instance, analysis of arsenic (As) in SiGe requires ultra‐high mass resolution (MR) to resolve the mass interferences to As and AsSi. Unfortunately, the ultra‐high MR is achieved at the cost of sensitivity for magnetic sector SIMS. Especially in the case of low‐dose As implantation, 75As28Si− should be monitored to ensure enough dynamic range. But the required MR to resolve mass interference of 74Ge29Si− to 75As28Si− is too high for all types of SIMS systems. In this work, a numerical approach has been developed to eliminate the mass interference to AsSi based on the dependence of interference ion intensity on Ge concentration. An undoped SiGe sample with a Ge fraction of 0.128 was used as the reference sample to determine the dependence of interference ion intensity on Ge‐contained reference ions intensity. Interpolation algorithm was applied to minimize the deviation caused by the test time difference. The effectiveness of two interpolation algorithms, linear and exponential interpolation, was evaluated in this paper. Gaussian‐like profiles of As implantation with the dose of 3.6E13 at/cm2 and 1E15 at/cm2 were obtained with this numerical approach. The profile of 1E15 at/cm2 As implantation agreed quite well with that obtained with ultra‐high mass resolution, and achieved at least two orders of improvement in the dynamic range. Copyright © 2010 John Wiley &amp; Sons, Ltd.

High Temperature Thermoelectric Properties of Nano-Bulk Silicon and Silicon Germanium

AbstractPoint defect scattering via the formation of solid solutions to reduce the lattice thermal conductivity has been an effective method for increasing ZT in state-of-the-art thermoelectric materials such as Si-Ge, Bi2Te3-Sb2Te3 and PbTe-SnTe. However, increases in ZT are limited by a concurrent decrease in charge carrier mobility values. The search for effective methods for decoupling electronic and thermal transport led to the study of low dimensional thin film and wire structures, in particular because scattering rates for phonons and electrons can be better independently controlled. While promising results have been achieved on several material systems, integration of low dimensional structures into practical power generation devices that need to operate across large temperature differential is extremely challenging. We present achieving similar effects on the bulk scale via high pressure sintering of doped and undoped Si and Si-Ge nanoparticles. The nanoparticles are prepared via techniques that include high energy ball milling of the pure elements. The nanostructure of the materials is confirmed by powder X-ray diffraction, transmission electron microscopy, scanning electron microscopy, and dynamic light scattering. Thermal conductivity measurements on the densified pellets show a drastic 90% reduction in the lattice contribution at room temperature when compared to doped single crystal Si. Additionally, Hall effect measurements show a much more limited degradation in the carrier mobility. The combination of low thermal conductivity and high power factor in heavily doped n-type nanostructured bulk Si leads to an unprecedented increase in ZT at 1275 K by a factor of 3.5 over that of single crystalline samples. Experimental results on both n-type and p-type Si are discussed in terms of the impact of the size distribution of the nanoparticles, doping impurities and nanoparticle synthesis processes.

Silicon-based thin films as bottom electrodes in chalcogenide nonvolatile memories

The effect of the electrical resistivity of a silicon–germanium (SiGe) thin film on the phase transition in a GeSbTe (GST) chalcogenide alloy and the manufacturing aspect of the fabrication process of a chalcogenide memory device employing the SiGe film as bottom electrodes were investigated. While p-type SiGe bottom electrodes were formed using in situ doping techniques, n-type ones could be made in a different manner where phosphorus atoms diffused from highly doped silicon underlayers to undoped SiGe films. The p–n heterojunction did not form between the p-type GST and n-type SiGe layers, and the semiconduction type of the SiGe alloys did not influence the memory device switching. It was confirmed that an optimum resistivity value existed for memory operation in spite of proportionality of Joule heating to electrical resistivity. The very high resistivity of the SiGe film had no effect on the reduction of reset current, which might result from the resistance decrease of the SiGe alloy at high temperatures.

Thermal stability of NiPt- and Pt-silicide contacts on SiGe source/drain

NiPt (10% Pt) and Pt were investigated as alternatives to Ni for contact formation to SiGe (20%) source/drain. The germanosilicide phase formation and morphology were studied by means of sheet resistance measurements, X-ray diffraction (XRD) analysis and scanning electron microscopy (SEM) inspection. From isothermal anneals it is found that NiPt- and Pt-germanosilicide have better thermal stability compared to Ni-germanosilicide. Improved thermal stability is observed for Ni-, NiPt- and Pt-germanosilicide on B doped SiGe as compared to undoped SiGe. The degradation mechanism of NiPt- and Pt-germanosilicide films on SiGe is morphological degradation while the film is still in the mono-(germanosilicide) phase.

Embedded Source/Drain SiGe Stressor Devices on SOI: Integrations, Performance, and Analyses

A detailed investigation of embedded source/drain SiGe stressors (eSiGes) on a silicon-on-insulator substrate for pMOS performance enhancement is presented. It is found that the integration with undoped SiGe epitaxy suffers strain relaxation from a postepitaxy implantation. SiGe growth with in situ doping is able to retain high strain for carrier mobility enhancement. For doped eSiGe integration with a proper thermal sequence, 20% pMOS drive current improvement is demonstrated. Quantitative analyses of contributions from mobility enhancement and device exterior resistance reduction to the performance improvement are also discussed

Novel Process Development for Bilayer Embedded SiGe Source/Drain Formation

We have developed a new technique of bilayer embedded SiGe epitaxy in order to suppress the degradation of short channel characteristics in PFETs. We have found that the SiGe growth rate near the recess side wall increased when using a high SiH2Cl2 flow at high pressure. It enabled 1st conformal undoped SiGe layer growth for the recess shape. For the 2nd SiGe layer, we used an appropriate B2H6flow rate for good morphology. XAFS revealed that the 2nd nearest neighbors of Ge became distorted when the incorporated amount of B increased. In addition, we developed a Simultaneous condition switching technique for forming bilayer embedded SiGe.

Temperature dependence of electron and hole mobilities in heavily impurity-doped SiGe single crystals

Heavily impurity-doped single crystals of SixGe1−x alloy with the composition 0.84&amp;lt;x&amp;lt;1 and large-grained polycrystals with x=0.80 were grown by the Czochralski technique. The Hall-coefficient measurements of the electron and hole mobilities in the grown crystals were carried out in the temperature range of 300–1000K and compared with those in undoped SiGe. The Hall mobilities of electrons and holes in SiGe with a carrier concentration of 1019–1020cm−3 both show a Tn, n∼1, temperature dependence up to elevated temperatures. This indicates that the carrier transport process is mainly rate controlled by charged impurity scattering. In single-crystal SiGe free from grain-boundary effects, the hole mobility increases with decreasing Si content at least up to 0.84 and the electron mobility is greater than in Si and polycrystalline SiGe. These results suggest that scattering processes in alloy semiconductors are more complicated than previously thought.

Effects of collector heterojunction displacement from its p–n junction on the unilateral power gain at 10 GHz in SiGe HBTs

The design of SiGe heterojunction bipolar transistors for high frequency (10 GHz), high power applications has been investigated by numerical device modelling using a commercial simulator. For the SiGe base layer, boron outdiffusion can give rise to displacement of the base-collector p–n junction from the collector heterojunction, which contributes to the development of a parasitic barrier in the conduction band. In this paper, using a Gaussian distribution for the base's boron profile, we examine the effects of the device's epitaxial layer design on the device's unilateral power gain at 10 GHz and its relation to this barrier. Degradation in the device's microwave power gain was found to correlate with formation of the collector junction parasitic barrier, where the barrier height was found to depend upon the extent of the p–n junction displacement from the heterojunction, the Ge concentration in the base and the dc bias point. Trade-offs in device design to reduce its sensitivity to outdiffusion were examined including the use of undoped SiGe spacer layers, increased collector doping and the insertion of a thin, n+ layer at the collector junction.

The influence of carbon on the properties of Si/SiGe heterostructures

Si/SiGe/SiGe:C/SiGe/Si heterostructures are investigated by Raman spectroscopy, electroreflectance method, and secondary-neutral mass spectrometry. It is shown that doping of a SiGe layer lying between undoped SiGe layers with C (1.5%) leads to almost complete stress relaxation in the doped layer. It is found that high-temperature photon annealing is responsible for a partial stress relaxation in the lower SiGe buffer layer. However, such annealing increases the Si content in this layer. Low-temperature treatment in the radio-frequency (RF) hydrogen plasma leads to considerable stress relaxation in the lower buffer layer without varying its composition. The results obtained from the electroreflectance and secondary-neutral-mall spectra correlate with the Raman spectroscopy data.