Unclamped Inductive Switching Conditions Research Articles

Reliability investigation of repeated unclamped inductive switching in a diode-clamped SiC circuit breaker

This paper investigates the reliability of a solid-state circuit breaker with a clamped SiC diode as avalanche voltage after repeated cutoff operations. In solid-state circuit breakers, a clamping element is connected in parallel with a power semiconductor switch to divert the cutoff current. The SiC merged PiN Schottky (MPS) diode is one of the candidates for clamping elements in solid-state circuit breakers because of its high avalanche tolerance and good robustness after the shocks. Reliability tests indicate that no significant electrical characteristics are found for both the SiC MOSFET and the SiC MPS diode in the proposed circuit breaker, even after more than 10,000 unclamped inductive switching (UIS) cycles. These results are based on a 400V, 50A DC distribution system with the UIS condition. The results show that the SiC MPS diode works well as a clamped element for the long-term reliability of the solid-state circuit breaker.

Benchmarking the robustness of Si and SiC MOSFETs: Unclamped inductive switching and short-circuit performance

The reliability and robustness of power devices are key areas of research for increasing the adoption of wide bandgap power semiconductors. This paper benchmarks the robustness under short-circuit (SC) and unclamped inductive switching (UIS) of 650 V SiC trench MOSFETs, SiC planar MOSFETs and silicon super-junction MOSFETs. The performance is characterised at 75 °C and 150 °C and the results show that the SiC MOSFETs have reduced temperature sensitivity under both SC and UIS conditions, which will be beneficial from the application point of view. In the case of the silicon MOSFET, increasing the temperature enhances the short-circuit withstand time as the peak short-circuit current is reduced. The opposite trend is observed for UIS, with a reduction of robustness as the temperature is increased. The absolute SC and avalanche energies are lower for the SiC MOSFETs, but if the chip areas are considered, the energy densities are higher in the SiC MOSFETs, with the SiC Trench having a superior critical SC energy and the SiC planar having a higher avalanche energy density. The higher critical SC and UIS energy densities in SiC MOSFETs, together with their higher thermal resistances result in higher peak junction temperatures and clear hotspots are identified using Finite Element simulations.

Numerical study of destruction phenomena for punch-through IGBTs under unclamped inductive switching

In this paper, a numerical description of the ruggedness of punch-through (PT) IGBTs under the unclamped inductive switching (UIS) has been proposed using two-dimensional (2D) simulations with the calibration to experimental results. The UIS capability is an important design factor of device structures for the purpose of screening defects produced during the wafer process. The local hot spot due to the current filament three-dimensionally (3D) distributed over the chip area requires 3D simulations to reproduce the current density of the filament and its behavior leading to the device destruction; however, it is difficult to simulate such a large area with an appropriate mesh size and a boundary condition. To provide a possible solution of this technical issue, 2D simulations using large scale multi-cell structures with the increased current density has been proposed to reproduce experimental results without resorting to 3D simulations. With this approach, not only destructive phenomena including the UIS ruggedness and the latch-up failure mode have been reproduced, but also the device internal state leading to the destruction has been revealed. The spatial distribution of the electric potential and the lateral electric field during the UIS condition is shown to be a key role determining the current filament width and the UIS ruggedness. Besides, the high frequency oscillation of the collector voltage during the UIS observed by experiments has been analyzed and has found to be related with the hopping motion of the current filament from a cell to its neighboring cell of the device.

Robustness and Balancing of Parallel-Connected Power Devices: SiC Versus CoolMOS

Differences in the thermal and electrical switching time constants between parallel-connected devices cause imbalances in the power and temperature distribution, thereby reducing module robustness. In this paper, the impact of electrothermal variations (gate and thermal resistance) between parallel-connected devices on module robustness is investigated for 900-V-CoolMOS and 1.2-kV-SiC MOSFETs under clamped inductive switching (CIS) and unclamped inductive switching (UIS). Under CIS, the difference in the steady-state junction temperature ( ${\bm {\Delta }}{{\bm {T}}_{\bm {J}}}$ ) and switching energy ( ${\bm {\Delta }}{{\bm {E}}_{{\bf SW}}}$ ) between the parallel-connected devices for a given difference in the gate and thermal resistance ( ${\bm {\Delta }}{{\bm {R}}_{\bm {G}}}$ and ${\bm {\Delta }}{{\bm {R}}_{{\bf TH}}}$ ) is used as the metric for determining robustness to electrothermal variations, i.e., how well the devices maintain uniform temperature inspite of switching with different rates and thermal resistances. Under UIS conditions, the change in the maximum avalanche current/energy prior to device failure as a function of the ${\bm {\Delta }}{{\bm {T}}_{\bm {J}}}$ and ${\bm {\Delta }}{{\bm {R}}_{\bm {G}}}$ between the parallel-connected devices is used as the metric. Under both CIS and UIS, SiC devices show better performance with minimal negative response to electrothermal variations between the parallel-connected devices. Finite-element models have also been performed showing the dynamics of BJT latch-up during UIS for different technologies.

Electrical Parameters Degradations and Optimizations of SOI-LIGBT Under Repetitive Unclamped-Inductive-Switching Conditions

The electrical parameters degradations for the lateral insulated gate bipolar transistor on a silicon-on-insulator substrate (SOI-LIGBT) under repetitive unclamped inductive switching (UIS) conditions have been experimentally investigated using the pulsing anode (also called the collector) inrush current stress. The main degradation mechanism is identified to be hot holes injection and trapping into the field oxide under the polygate terminal. In this way, though the monitored threshold voltage ( $V_{\mathrm {th}})$ shift is not obvious, the ON-state linear anode current ( $I_{\mathrm {alin}})$ is increased with stressing time due to the induced mirror carriers, and the OFF-state breakdown voltage is largely decreased because of the increase in the peak electrical field in the SOI layer. Thereby, the parameters degradations induced by repetitive UIS conditions must be taken into consideration during SOI-LIGBT design and lifetime evaluation. Finally, a novel SOI-LIGBT structure with double high-voltage wells has been presented to optimize the degradations.

3-D electrothermal simulation of active cycling on smart power MOSFETs during short-circuit and UIS conditions

Active cycling of power devices operated in harsh conditions causes high power dissipation, resulting in critical electrothermal and thermo-mechanical effects that may lead to catastrophic failures. This paper analyzes the ageing-induced degradation of the chip metallization of a power MOSFET and its impact on the device robustness during short-circuit and unclamped inductive switching tests. A 3-D electrothermal simulator relying on a full circuit representation of the whole device is used to predict the influence of various ageing levels. It is found that ageing can jeopardize the robustness of the transistor when subject to short-circuit conditions due to the exacerbated de-biasing effect on the gate-source voltage distribution; conversely, this mechanism does not arise under unclamped inductive switching conditions. This allows explaining the difference in time-to-failure experimentally observed for the transistors subject to these tests and dissipating the same energy.

Improved Electrothermal Ruggedness in SiC MOSFETs Compared With Silicon IGBTs

A 1.2-kV/24-A SiC-MOSFET and a 1.2-kV/30-A Si-Insulated gate bipolar transistor (IGBT) have been electrothermally stressed in unclamped inductive switching conditions at different ambient temperatures ranging from −25 °C to 125 °C. The devices have been stressed with avalanche currents at their rated currents and 40% higher. The activation of the parasitic bipolar junction transistor (BJT) during avalanche mode conduction results from the increased body resistance causing a voltage drop between the source and body, greater than the emitter-base voltage of the parasitic BJT. Because the BJT current and temperature relate through a positive feedback mechanism, thermal runaway results in the destruction of the device. It is shown that the avalanche power sustained before the destruction of the device increases as the ambient temperature decreases. SiC MOSFETs are shown to be able to withstand avalanche currents equal to the rated forward current at 25 °C, whereas IGBTs cannot sustain the same electrothermal stress. SiC MOSFETs are also shown to be capable of withstanding avalanche currents 40% above the rated forward current though only at reduced temperatures. An electrothermal model has been developed to explain the temperature dependency of the BJT latchup, and the results are supported by finite-element models.

Dynamic avalanche behavior of power MOSFETs and IGBTs under unclamped inductive switching conditions

The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching (UIS) conditions is measured. This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT, which occur at different current conditions. The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor, which leads to the deterioration of the avalanche reliability of power MOSFETs. However, the results of the IGBT show two different failure behaviors. At high current mode, the failure behavior is similar to the power MOSFETs situation. But at low current mode, the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.

A Robust 3-D Structure for Superjunction VDMOS Under Unclamped Inductive Switching Condition

A novel 3-D structure for Superjunction (SJ) VDMOS which results in high avalanche energy (EAS) under unclamped inductive switching condition without degrading the ON-state current capability is reported in this paper. The proposed structure fabricated in deep trench technology has segmented n+ source region and strip gate. The novel structure can suppress the hole current path beneath the n+ source region under avalanche breakdown condition because of the p+ region which is located between the segmented n+ source regions. In order to verify the mechanism, numerous 3-D simulations are performed using Sentaurus TCAD. As a result, the measurement shows that the robust deep trench SJ-VDMOS improved the EAS by more than six times compared with the conventional structure.

Analysis of current distribution on IGBT under unclamped inductive switching conditions

The current filament movement within and between emitter pads of an IGBT under unclamped inductive switching conditions was measured. This measurement was achieved by using a test setup capable of measuring the emitter current distributions in nine independent points over the active area of the IGBT. The measured filament speed into the pads was between the range of 150–400μm/μs, and the filament speed increases by increasing the collector current. Moreover, current hopping phenomenon was observed between non-neighbouring emitter pads as well.

A novel superjunction MOSFET with improved ruggedness under unclamped inductive switching

The ruggedness of a superjunction metal—oxide semiconductor field-effect transistor (MOSFET) under unclamped inductive switching conditions is improved by optimizing the avalanche current path. Inserting a P-island with relatively high doping concentration into the P-column, the avalanche breakdown point is localized. In addition, a trench type P+ contact is designed to shorten the current path. As a consequence, the avalanche current path is located away from the N+ source/P-body junction and the activation of the parasitic transistor can be effectively avoided. To verify the proposed structural mechanism, a two-dimensional (2D) numerical simulation is performed to describe its static and on-state avalanche behaviours, and a method of mixed-mode device and circuit simulation is used to predict its performances under realistic unclamped inductive switching. Simulation shows that the proposed structure can endure a remarkably higher avalanche energy compared with a conventional superjunction MOSFET.

Evaluation of the ruggedness of power DMOS transistor from electro-thermal simulation of UIS behaviour

High-voltage power MOSFETs have been widely used in switching mode power supply circuits as output drivers for industrial and automotive electronic control systems. However, as the device size is reduced, the energy handling capability is becoming a very important issue to be addressed together with the trade-off between the series on-resistance RON and breakdown voltage VBR. Unclamped inductive switching (UIS) condition represents the circuit switching operation for evaluating the “ruggedness”, which characterizes the device capability to handle high avalanche currents during the applied stress. In this paper we present an experimental method which modifies the standard UIS test and allows extraction of the maximum device temperature after the applied standard stress pulse vanishes. Corresponding analysis and non-destructive prediction of the ruggedness of power DMOSFETs devices supported by advanced 2-D mixed mode electro-thermal device and circuit simulation under UIS conditions using calibrated physical models is provided also. The results of numerical simulation are in a very good correlation with experimental characteristics and contribute to their physical interpretation by identification of the mechanism of heat generation and heat source location and continuous temperature extraction.