Thermometer Code Research Articles

A low-power 100MS/s Flash ADC with Thermometer code encoding technique for automotive applications

A low-power 100MS/s Flash ADC with Thermometer code encoding technique for automotive applications

Design of Wallace Tree Encoder for Flash ADC

Analog to digital converter plays a very important role in today’s digitized world as they have wide range of applications. Wallace tree encoder is an effective hardware implementation in VLSI circuits that is utilized for the analogue to digital conversion process. The Wallace tree encoder transforms thermometer code into binary code in an ADC. The suggested flash digital to analogue converter confirmed the energy, and speed. The proposed technique provides Less Delay, Less Power Consumption, and a lesser number of transistors compared to existing techniques. In this project, the proposed transmission gate full adder technique provide Less Delay, Less Power Consumption, Better Power Delay Product and a lesser number of transistors. The proposed encoder is made to count the 1s available to the logic gates for designing ROM encoders and fat tree conversion. The power may be conserved by building a low power, high performance Wallace tree encoder implementing transmission gate logic and modified full adders since Wallace tree encoder uses more power. The proposed system focuses at lowering the transistor count to improve power efficiency and delay comparator, and it is effective in minimizing the bubble errors. The Wallace tree encoder is designed by using transmission gate based full adder circuits. The proposed designs are designed and simulated using LTspice Tool with 45nm CMOS technology. The power consumption of the encoder circuit must be decreased in order to create a low power Flash ADC. The power consumption of this encoder changes noticeably when the internal full adder circuit is modified

Design of High Performance and Power Efficient Flash ADC

In this paper, Flash Analog to digital converter is implemented. The designed Flash ADC consists of a resistive ladder network, comparators, the thermometer to a binary encoder and the entire design is carried out using Tanner tools employing 180nm technology. The reference voltage applied to the resistive ladder network is 1.8V. A two-stage operational amplifier is used as a comparator in the flash ADC. Here, we are modifying the structure of operational Amplifier using Power Gating Technique. Binary code is obtained from the thermometer code by utilizing a Mux based encoder by designing the MUX in domino Logic. The major problem that usually appears in flash ADC is as the number of resolution bits increases, the Area, as well as the power consumption of the circuit, also increases. In this paper, we principally concentrated to lessen the propagation delay of the ADC by optimizing encoder circuitry. With the purpose of reducing latency, Encoder is implemented using 2:1 mux based on Pseudo NMOS Logic. Performance parameters of Flash ADC such as delay as well as average power are calculated and compared.

Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks-an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it.

A Highly Linear and Flexible FPGA-Based Time-to-Digital Converter

Time-to-Digital Converters (TDCs) are major components for the measurements of time intervals. Recent developments in Field-Programmable Gate Array (FPGA) have enabled the opportunity to implement high-performance TDCs, which were only possible using dedicated hardware. In order to eliminate empty histogram bins and achieve a higher level of linearity, FPGA-based TDCs typically apply compensation methods either using multiple delay lines consuming more resources or post-processing, leading to a permanent loss of temporal information. We propose a novel TDC with a single delay line and without compensation to realize a highly linear TDC by encoding the states of the delay lines instead of the thermometer code used in the conventional TDCs. The experimental results show our states-based approach achieves an improved Differential Non-Linearity (DNL) of [-0.998, -1.533] for time resolution of 5.00 ps, [-0.44,0.49] for 10.04 ps, [-0.16, 0.19] for 21.65 ps, [-0.10, 0.11] for 43.87 ps, [-0.06, 0.07] for 64.12 ps, and [-0.07, 0.05] for 87.73 ps, whilst no empty bins have been observed. To our knowledge, the achieved raw linearity together with the zero empty bins and a simple delay line structure exceeds previously reported of the FPGA-based TDCs.

A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS

This paper presents a high-current calibration-free analog-digital hybrid controlled LDO for large-area digital load. The proposed architecture has the advantages of an analog controller (continuous and high DC accuracy) with distributed digital power transistors (flexible and scalable for high current applications). Distinctive from the conventional digital LDOs that directly quantize the output voltage, the proposed LDO utilizes an error amplifier (EA) to pre-amplify the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm {OUT}}$ </tex-math></inline-formula> error. Then, a 5-bit time-to-digital converter (TDC) quantizes the processed analog error signal subsequently transformed into a thermometer code that directly controls the distributed digital power transistors. This design can pull off high DC accuracy even without calibration. Besides, we implement an auxiliary constant current (ACC) circuit to solve reliability issues and to improve the stability under a large voltage dropout. Fabricated in a 28-nm bulk CMOS process with a 1.2-A load capability, the proposed LDO achieves 2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{V}$ </tex-math></inline-formula> /mA load regulation and close to 1.5% output accuracy. By employing a wide bandwidth EA and a fast TDC, the hybrid LDO can obtain a fast transient response. The measured undershoot is 70 mV with a 0.6-A load step within 10-ns edge time, and the output voltage can scale from 0.6 V to 0.9 V within 30 ns.

In-Memory Computation With Improved Linearity Using Adaptive Sparsity-Based Compact Thermometric Code

The article presents an efficient static random access memory (SRAM)-based in-memory computation (IMC) architecture which is capable of performing image classification with improved linearity. In this work, we proposed a thermometric code-based IMC (TC-IMC) to perform multibit multiply-and-accumulate (MAC) operations with improved linearity. An input sparsity-aware compact thermometric code approach is proposed to reduce the number of SRAM bitcells compared to the thermometric code-based encoding without loss of accuracy in the MAC operation. We proposed an optimal sampling time to improve the linearity of the TC-IMC MAC operation with maximum signal margin (SM) based on the detailed nonlinearity analysis of 8T SRAM-based TC-IMC architecture. The test chip measurement results in 180 nm process show that the proposed TC-IMC has 72% better linearity than the traditional IMC. The measured results on 100 Modified National Institute of Standards and Technology (MNIST) and CIFAR-10 test images show an accuracy of 97% and 87%, respectively. In addition, the proposed TC-IMC architecture achieves MAC compute latency of 25 ns, GOPS/kb (normalized to 1 b <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 1 b) of 29.8, and energy efficiency of 2.3 TOPS/W. The simulation result of the entire 10000 MNIST and CIFAR-10 images considering process variation effects shows an accuracy of 98.7% and 90.4%, respectively.

Ultra-Low-Power Modulo Adder with Thermometer Coding for Uncertain RNS Applications

The residue numeral system (RNS) is a numerical representation of integers based on modulo values. The RNS makes computing systems more efficient in terms of speed, power, energy, area, and other considerations. In recent years, the RNS has focused on a variety of topics, including digital signal and image processing, cryptography, embedded systems (ESs), communications, and the Internet of Things (IoT), among others. Forward and reverse converters, as well as arithmetic units in the channels, all use modular addition. In low-power ESs, thermometer coding (TC) has lately been utilized to reduce uncertainty. The thermometer code (TC) is more energy-efficient and consumes less power for modulo addition as compared to binary adders. Based on TC, the proposed research develops a power-efficient modular adder. The proposed design is simulated using Cadence’s NC launch encounter tool. In comparison with conventional modular adders, the proposed modular adder consumes 40% and 35% less power for one-hot coding modulo adder and thermometer code residue (TCR) modulo adder, respectively.

Application of Huffman Algorithm and Unary Codes for Text File Compression

Technique in carrying out data compression is an important point in technological developments. With compression in data in the form of text can include many uses, including for data transfer, copying and for backing up data. From its uses, this aspect is important for data security. There are many compression techniques on the data, including using huffman algorithms and unary code. One of its applications will be implemented on a text data that is widely used by digital actors in storing important data. The data must not be known by unauthorized parties in accessing the data. Therefore, huffman algorithms and unary code can solve this problem. By compressing the selected data also encrypts it as an extra security. The Huffman algorithm is a lossless compression algorithm or a technique that does not change the original data, by converting the unit of data content into bits. So this algorithm is widely used in the compression process. The Unary Codes algorithm is also a lossless compression technique that is generally used by combining several modification techniques. In this unary codes algorithm, each symbol in the string will be searched for its frequency. Then sorted from the last order (descending). The use of these two text data compression techniques results in a file size that is smaller than the original but can be returned to the original data

A 19 ps Precision and 170 M Samples/s Time-to-Digital Converter Implemented in FPGA with Online Calibration

This paper presents a 19 ps precision and 170 M samples/s time-to-digital converter (TDC) in FPGA. Through the direct count method and tapped delay line method, the coarse count and fine count can be extracted, respectively. The direct count is realized by the 350 M clock and the tapped delay line is constructed by the CARRY4 block. The ones-counter encoder is used to convert the thermometer code with bubble errors into binary code, which is applicable to all the FPGA chips. This work not only explains the schematic of the ones-counter encoder, but also shows how to configure it. Owing to the inconsistency of delay elements caused by process, bin-by-bin calibration is utilized to improve the differential nonlinearities (DNL) and integral nonlinearities (INL) of the TDC. A novel method was developed to compensate the influence of voltage and temperature. As the delay elements vary with voltage and temperature, a frequency counter is used to extrapolate and compensate its effect on the delay line. All of the above strategies use online calibration and improve the precision and sampling rate of TDC. The experimental results show the least significant bit (LSB) achieves 17.4 ps, the DNL is within [−0.90, 1.67] LSB, and the INL is in the range of [−1.90, 3.31] LSB.

An effective GDI (Gate Diffusion Input) Based 16- bit Shift Register Design for Power and Area Optimization

Abstract: Sequential circuit design is heavily influenced by power consumption and area reduction. Mainly consisted is shown here. Rather than using flip flops, pulsed latches are used to limit the amount of space these utilize. The shift register uses a minimal number of pulsed clock signals by combining the latches into numerous sub shifter registers and using Multiplexer and additional temporary storage latches. Multiple non-overlap delayed pulsed clock signal schemes are presented for data synchronization in a multi bit shift register to decrease power consumption. In order to maintain the current system, Tanner SEDIT will be used with Taiwan Semiconductor (TSMC) 0.18mm technology. Designing low-power digital combinational circuits using Gate Diffusion Input(GDI) is a common practice nowadays. When used in particular operating conditions, the GDI approach restores the in-cell swing by implementing sophisticated logic functions on two transistors. This method reduces power consumption, propagation latency, and digital circuit size while maintaining low complexity of logic design. Dual Edge Triggered Flip Flop(DETFF) implementation using GDI technology is introduced as an improvement to the shift register design. This idea also takes into account time restrictions, which can be reduced with the least amount of management. Keywords: Shift Register, Thermometer Code, Gate Diffusion Input, Dual Edge Triggered Flip-Flop, Propagation latency.

Compact unary coding for bosonic states as efficient as conventional binary encoding for fermionic states

We introduce a unary coding of bosonic occupation states based on the famous "balls and walls" counting for the number of configurations of $N$ indistinguishable particles on $L$ distinguishable sites. Each state is represented by an integer with a human readable bit string that has a compositional structure allowing for the efficient application of operators that locally modify the number of bosons. By exploiting translational and inversion symmetries, we identify a speedup factor of order $L$ over current methods when generating the basis states of bosonic lattice models. The unary coding is applied to a one-dimensional Bose-Hubbard Hamiltonian with up to $L=N=20$, and the time needed to generate the ground state block is reduced to a fraction of the diagonalization time. For the ground state symmetry resolved entanglement, we demonstrate that variational approaches restricting the local bosonic Hilbert space could result in an error that scales with system size.

Development of an on-chip configurable DAC module for monolithic active pixel sensor

This paper describes an on-chip configurable Digital to Analog Converter (DAC) module for monolithic active pixel sensor. The DAC module consists of four 10-bit voltage DACs, seven 8-bit current DACs, a bandgap circuit, and a configure interface. The voltage DAC is implemented with an R-2R resistor ladder network, and each LSB corresponds to 3 mV. The current DAC is in the current-steering type with a thermometer code. Each LSB of the current DAC corresponds to 10 nA. The bandgap circuit provides a stable, temperature-independent reference voltage of 1.25 V to the DACs. All the DACs can be accessed and configured with the configure interface. The DAC module covers 3074 µm × 400 µm, and the total power consumption is 46.2 mW. This paper will discuss the design and performance of this DAC module.

A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR

This article presents a 50-Gb/s optical transmitter (TX), consisting of a 40-nm distributed CMOS driver and a 180-nm silicon-photonic modulator. A lumped-segment Mach–Zehnder modulator (LS-MZM) is developed for high bandwidth (BW) four-level pulse amplitude (PAM-4) modulation. A multi-segment driver with limiting outputs is co-designed, which is distributed into each LS-MZM segment. By grouping these LS-MSM segments in a thermometer code, high-linearity modulation is realized without the need of power-hungry high-swing linear drivers. To improve the optical PAM-4 signal integrity, in-segment multiplexing along with clock phase interpolation is adopted to synchronize the electrical and optical signals across all segments. The hybrid coupling between the driver and modulator is devised to boost the BW of the high-speed data path, while a half-rate clock and data recovery (CDR) circuit is integrated to remove the accumulated jitter. Measurements show that the TX exhibits an extinction ratio (ER) of up to 9.8 dB and a 0.99 ratio of the level mismatch. A figure-of-merit (FoM) of 1.39 pJ/bit/dB corresponds to a 682-mW power, which can be further reduced by 40%, at the cost of a degraded ER of 4 dB. The PAM-4 CDR helps to achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; 10^{-12}$ </tex-math></inline-formula> BER and >0.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{U}I_{\mathrm {pp}}$ </tex-math></inline-formula> jitter tolerance (JTOL) from 10 to 100 MHz.

A Cortical Learning Machine for Learning Real-Valued and Ranked Data

The cortical learning machine (CLM) introduced in [1-3] is a low-order computational model of the neocortex. It has the real-time, photogragraphic, unsupervised, and hierarchical learning capabilities, which existing learning machines such as the multilayer perceptron and convolutional neural network do not have. The CLM is a network of processing units (PUs) each comprising novel computational models of dendrites (for encoding), synapses (for storing code covariance matrices), spiking/nonspiking somas (for evaluating empirical probabilities and generating spikes), and unsupervised/supervised Hebbian learning schemes. In this paper, the masking matrix in the CLM in [1-3] is generalized to enable the CLM to learn ranked and real-valued data in the form of the binary numbers and unary (thermometer) codes. The general masking matrix assigns weights to the bits in the binary and unary code to reflect their relative significances. Numerical examples are provided to illustrate that a single PU with the general masking matrix is a pattern recognizer with an efficacy comparable to those of leading statistical and machine learning methods, showing the potential of CLMs with multiple PUs especially in consideration of the aforementioned capabilities of the CLM.

The XOR-MAJ Thermometer-to-Binary Encoder Structure Stable to Bubble Errors

Thermometer-to-binary encoder is an essential part of a flash analog-to-digital converter (ADC). Errors in the thermometer code must be adequately handled by the encoder to avoid performance degradation. The presented concept of a reference encoder helps to classify errors and to compare error impact on real encoders. A new encoder structure is proposed as an alternative to the adder-based encoder known for its error robustness. Simulation in MATLAB reveals that the proposed encoder structure is as resistant to single and double errors in the input code as the adder-based one. Encoders were synthesized and simulated in 65-nm CMOS using Cadence design tools. For bit widths from 4 to 8, the proposed circuit is 10-12% larger in transistor count but has a 34-45% lower delay than an adder-based circuit which makes its use practical.

A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm

PurposeThe purpose of this paper is to present the performance of an 8-bit hybrid DAC which is suitable for wireless application or part of a built-in test block for ADC. The hybrid architecture used is the combination of thermometer coding and binary-weighted resistor architectures.Design/methodology/approachThe conventional DAC topology performance tends to degrade at high-resolution applications. A hybrid topology, which combines an equal number of bits of thermometer coding and binary-weighted resistor architectures operating at higher sampling frequency, was proposed in this work. The die was fabricated in 180 nm CMOS process technology with a supplied voltage of 1.8 V.FindingsMeasured results showed that the DNL and INL errors are within −1 to +1 LSB and −0.9 to +0.9 LSB, respectively for the input range of 0.9 V at the clock rate of 200 MHz, and this DAC was proven monotonic. This 0.068 mm2 DAC consumed 12.6 mW for the data conversion.Originality/valueThis paper is of value in showing the equal division of bits from thermometer coding and binary-weighted resistor architectures provides smaller die size and enhances the performance of hybrid DAC, in terms of linearity, which are DNL and INL errors and guarantees monotonicity at higher sampling frequency.

Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing

Neural network (NN) computing contains a large number of multiply-and-accumulate (MAC) operations. The performance of NN accelerator is limited with the traditional von Neumann architecture due to the tremendous off-chip memory accesses. Resistive random-access memory (ReRAM)-based crossbars can naturally perform matrix–vector multiplication (MVM) operations and are well suitable for NN accelerators. In the existing ReRAM-based NN accelerators, the synaptic weights represented by the conductances of ReRAMs are mainly based on the binary coding. However, the imperfect fabrication process combined with stochastic filament-based switching leads to resistance variations of ReRAMs, which can significantly alter the weights in binary synapses and degrade the NN accuracy. Moreover, the NN accuracy further deteriorates with multilevel cells (MLCs) used for reducing hardware overhead. In this article, a novel unary coding of synaptic weights is proposed to overcome the resistance variations of MLCs and achieve reliable ReRAM-based neuromorphic computing. A variation-aware optimal mapping scheme is also proposed in compliance with the unary coding to guarantee high accuracy by leveraging a unique feature of unary coding—the existence of multiple ways to represent the same value. The optimal mapping obtains very small errors for weights with resistance variations of MLCs. Our simulation results show that under resistance variations, the proposed method achieves less than 0.08% and 3.43% accuracy loss on CIFAR10 and ImageNet, respectively, compared to the ideal accuracy. With each synaptic weight represented by four 2-b MLCs, the proposed method improves the accuracy over the traditional binary coding scheme by 83.39% and 87.6% for CIFAR10 and ImageNet, respectively.

Unary Coding Design for Simultaneous Wireless Information and Power Transfer With Practical M-QAM

Relying on the propagation of modulated radio-frequency (RF) signals, we can achieve simultaneous wireless information and power transfer (SWIPT) to support low-power communication devices. In this paper, we proposed a unary coding based SWIPT encoder by considering a practical M-QAM. Markov chains are exploited for characterising coherent binary information source and for modelling the generation process of modulated symbols. Therefore, both mutual information and the average energy harvesting performance at the SWIPT receiver are analysed in semi-closed-form. With the aid of the genetic algorithm, the sub-optimal codeword distribution of the coded information source is obtained by maximising the average energy harvesting performance, while satisfying the requirement of the mutual information. Simulation results demonstrate the advantage of the SWIPT encoder. Moreover, a higher-level unary code and a lower-order M-QAM results in higher WPT performance, when the maximum transmit power of the modulated symbol is fixed.

A 75-Mb/s RGB PAM-4 Visible Light Communication Transceiver System With Pre- and Post-Equalization

Visible light communication (VLC) technology employing light-emitting diodes (LEDs) as light sources has the advantages of using the license-free spectrum, being power and cost-efficient and having high security. However, common LED devices have the limitations of narrow bandwidths, nonlinear optical and frequency responses over different bias current levels, which cause inter-symbol interference and signal distortion, especially under high order modulation schemes with large current swings. In view of this, a compact PAM-4 VLC transceiver system employing a white LED as the light source with pre- and post-equalization is proposed. The white LED consists of a red, a green and a blue LED unit (RGB LED). Controlled by 3-bit thermometer codes, three separate drivers with feed-forward equalizers (FFEs) drive the RGB LED units to produce the PAM-4 optical signal. The driving currents from the three drivers with FFEs can be calibrated using digital and analog tunings to eliminate the differences in optical and frequency responses of the RGB LED units. A cascaded continuous-time linear equalizer (CTLE) is used at the receiver side as post-equalization to compensate for the narrow bandwidth of LED units. Based on experimental results, the proposed RGB PAM-4 VLC system can improve the highest achievable data rate by 1.67 times from 28 to 75 Mb/s using the pre- and post-equalization scheme.