Um CMOS Research Articles

A 99.99% current efficiency fast transient response capacitor-less LDO with feedforward compensation technique based on small-signal gain stage

An ultra-low power capacitor-less LDO with feedforward compensation technique based on the small-signal gain stage and composite transient enhancement structure is proposed. The feedforward compensation technique based on the small-signal gain stage reaches a low frequency zero ,by utilizing the compensating effect of the zero to relieve the adverse effects of the pole, thereby enhancing the stability and performance of the circuit. Furthermore, the small gain stage can adjust the quiescent current consumption,contributing to a significant reduction in system energy consumption. The proposed composite transient enhancement structure can reduce the transition time of the circuit, adjust the gain of the circuit under different operating conditions to achieve precise gain control and improve the transient performance of the system. The proposed LDO is designed using SMIC 0.18um CMOS process. The simulation results show the total quiescent current is 0.94uA and the current efficiency is up to 99.99%. The extremely low FoM value of 0.04 represents a good transient performance. Synthesizing the comparison of various parameters, the superiority of this design can be clearly concluded.

Design Of a High Gain Three-Stage CMOS Operational Amplifier for EEG Signal Processing

Recently, research on brain science has led to rapid development in Electroencephalography (EEG) signal processing. However, it is really hard to capture, amplify and measure the EEG signals from the human brain during the signal acquisition and amplification. Therefore, this paper introduces a newly-designed high gain three-stage CMOS operational amplifier to measure and amplify the EEG signals precisely. The main circuit structure is built in CoolSpice with the TSMC 0.18um CMOS technology. During the simulation in CoolSpice, the open-loop DC gain reaches to 90.04dB and its power consumption is around 19.8 mW. With the help of the frequency compensation applied in the circuit, the bandwidth of the op-amp achieves to 363Hz, which is able to amplify all sorts of EEG signals and measure them, and the phase margin with the value of 177 degrees, making the circuit system stable. This three-stage op-amp makes its circuit system stable and avoids the unnecessary oscillations during the EEG signal amplification, which lead to a precise measurement on EEG signals and provide the precise diagnosis for the patients.

A Highly Integrated Lab-on-a-CMOS Platform for Real-Time Monitoring of E. Coli Growth Kinetics.

Existing miniaturized and cost-effective solutions for bacterial growth monitoring usually require offline incubators with constant temperature to culture the bio-samples prior to measurement. Such a separated sample preparation and detection scheme requires extensive human intervention, risks contamination, and suffers from poor temporal resolution. To achieve integrated sample preparation and real-time bacterial growth monitoring, this article presents a lab-on-a-CMOS platform incorporates an optical sensor array, temperature sensor array, micro-heaters, and readout circuits. Escherichia coli's (E. coli) optimum growth temperature of 37 °C is achieved through a heat regulation system consisting of two micro-heaters and an on-chip temperature sensor array. A photodiode array with an in-pixel capacitive trans-impedance amplifier to reduce inter-pixel cross-coupling is designed to extract the optical information during bacterial growth. To balance the footprint, power consumption, and quantization speed, a 10 b column successive-approximation register (SAR)/single-slope (SS) dual-mode analog-to-digital converter (ADC) is designed to digitize the temperature and optical signals. Fabricated in a standard 0.18 um CMOS process, the proposed platform can regulate the sample temperature to 37 +/- 0.2/0.3 °C within 32 mins. Enabled by an on-chip heat regulation system and photodetectors, the prototype demonstrates a real-time monitoring of bacterial growth kinetics and antibiotic responses. Minute-level temporal resolution is achieved as this proposed platform is free of extensive and time-consuming human intervention. The proposed platform can be viably used in contamination sensitive applications such as antibiotic tests, stem cell cultures, and organ-on-chips.

Design of an integrated circuit with blanking technique for neural signal recording based on CMOS

Neural signals play a crucial role in unraveling the mysteries of the nervous system. However, due to their minute amplitudes in the range of microamperes and microvolts, recording these signals poses significant challenges, largely stemming from their vulnerability to noise interference. Thus, the development of neural signal acquisition circuits holds paramount importance. This paper presents a successful endeavor in designing an integrated circuit using 0.18um CMOS technology, which exhibits exceptional accuracy in recording neural signals. The circuit employs a combination of amplifiers and filters, while incorporating the innovative blanking technology to effectively eliminate unwanted noise. Remarkably, this design accomplishes an impressive gain of 88.437dB. Consequently, the circuit enables the accurate capture of nerve signals, thereby positioning itself as an ideal candidate for implantable neural signal detection devices. With its ability to overcome the hurdles associated with signal sensitivity and noise interference, this integrated circuit represents a significant advancement in the field of neural signal acquisition, holding immense potential for further exploration and application in neuroscientific research and medical interventions.

Design and Implementation of a Transmitter for IR-UWB Standard

In wireless communication, the Ultrawide Band (UWB) is a technique for achieving a higher data rate, low power consumption, and less complexity. Impulse Radio - Ultra-Wide Band (IR-UWB) uses the baseband signal technique, reducing circuit complexity and power consumption. This work proposes an IR-UWB transmitter block with low power and tunable bandwidth that meets the UWB regulations of LRP (Low-Rate Pulse) UWB. The transmitter proposed uses a time-interleaved architecture using 0.18um CMOS technology using Cadence Virtuoso, which consists of On Off Keying (OOK) Circuit for the four stages of a pulse generator that operates in 6.17GHz-9.10GHz. The width of the pulse is between 0.096ns to 0.162ns using a current steering inverter. The proposed transmitter block has an output swing of 30 mV at 1MHz input Pulse Repetition Frequency (PRF) and a maximum PRF of 1GHz, at a 1GHz pulse rate, the power consumption was measured to be 8.3 mW.

A Sigma-Delta Modulator with Single-Pole Double-Throw Analog Switch

In this paper, a high precision and high energy efficiency discrete-time switching capacitive 3-order Sigma-Delta modulator (SDM) is proposed. The SDM is applied to portable electroencephalograms (EEG) because of its little energy and good performance. The energy efficiency levels of the current mainstream modulator systems are analyzed and compared, and the CIFF modulator architecture which is most conducive to realizing high energy efficiency is selected. The single-loop CIFF structure is selected to give consideration to the accuracy and stability of the circuit. The circuit is implemented in a hierarchical structure, and a single-pole double-throw (SPDT) analog switch is adopted to overcome the difficulty of opening conventional CMOS analog switches at low supply voltages and the increase in threshold voltage Vth of NMOS devices due to the base bias effect. The proposed discrete-time Sigma delta ADC modulator is designed with SMIC 0.18um CMOS technology and achieves an SNDR of 101.6dB under a 1.8V power supply voltage and a signal bandwidth of 2kHz. The power consumption is 520uW and the significant bit (ENOB) is 16.58 bits.

CMOS Power Amplifier With Novel Transformer Power Combiner

A novel transformer combiner structure for wattlevel CMOS power amplifier design is presented in this letter. The proposed active skewered transformer (AST) utilizes the slab inductor as the secondary winding and overcomes the quality factor degradation issue when input cells are increased. Slab inductor has been previously used in the distributed active transformer (DAT) as the primary winding and achieved superior passive efficiency for the transformer combined CMOS power amplifier. However, we find that the slab inductor could be more beneficial as the secondary winding when we are aiming for higher output power from the CMOS power amplifier. The full-wave EM simulation has been performed and shows the advantage of AST over the conventional series-combining transformers (SCTs). Finally, a 2.4GHz CMOS power amplifier is designed based on the AST structure and fabricated in 0.18um CMOS process. The measured output power and power-added efficiency of the proposed power amplifier satisfying LTE specification with 5/20MHz bandwidth are recorded as 26.0/25.0dBm and 24.0/20.9%, respectively.

Design of analog front-end readout circuit for capacitive silicon micro gyroscope

To design a high-performance analog front-end readout circuit for capacitive silicon micromachined gyroscope, this paper presents electrical modeling of the silicon micromachined gyroscope according to its working characteristics, proposes to construct the amplitude and frequency range of the silicon micromachined gyroscope signal in the form of a capacitor array, and designs the capacitance readout circuit of the gyroscope based on this model. Based on the SMIC 0.18 um CMOS process, the electrical model and its capacitance readout circuit are designed and simulated in this paper. The results indicate that the capacitance readout circuit can accurately detect the equivalent variable capacitance signal of the gyroscope electrical model and transform it linearly into a voltage signal. The equivalent output noise of the overall analog front-end readout circuit is 80.11 nV/√Hz@6.4kHZ. The system resolution can reach 0.29 aF. As a result, the silicon micro gyroscope analog front-end circuit has a wide range of capacitive applications, high linearity, low noise, and broad market and application prospects. Hence, this topic is of great scientific significance.

Linearity Enhancement Techniques for PGA Design

This paper presents some techniques to improve the linearity of traditional resistive feedback PGAs. By utilizing the switched op-amp in the PGA, the MOS switches in the feedback resistor array can be eliminated and thus the PGA's linearity can be improved. The PGA's linearity is further improved with an additional capacitor, which is used for pre-charging the sampling capacitor to strengthen its capability to drive the sampling capacitor without any extra power consumption. The pre-charge technique is especially suitable for the case where the PGA drives a large sampling capacitance. Implemented in SMIC 0.18 um CMOS technology, the proposed PGA can achieve a gain of 0.5 or 1 and consumes 4.68 mW at a single 5 V supply with the switched output stage enabled. When driving a 20 pF sampling capacitor at a sampling frequency of 200 kHz, the simulation results show that the proposed PGA can give a 9 dBc improvement in SFDR of the sampled signal compared to the traditional PGA design and the SFDR can reach up to 114 dBc.

An NMOS transistor-based high-gain operational amplifier designed in 0.25-micron CMOS technology

This project describes in detail the process of designing and simulating at first a one stage folded cascode operational amplifier using 0.25 um CMOS Technology with the self-biasing scheme for the NMOS differential input stage is discussed here. The design of the required circuits is done using the LTspice simulator. We will see that the simulation results approximately matches with the desired and theoretically calculated performance values. We are changing width values to bring all the transistors of the circuit in saturation. Then two Stage Folded Cascode Operational Amplifier with Miller compensation technique for the NMOS input. The operational amplifiers circuit is designed with 0.25 µm CMOS Technology using LTspice software. The applied methodology to implement the circuit design for a given specification has clearly described including all the design equation has been presented. All the parameter like DC Gain and Phase Margin (PM) are presented and discussed. Finally, we have got after performance analysis that designed circuit based on NMOS input provide a 96 DC Gain.

Color performance of 0.8 um CMOS image sensor with CMY color filters

Modern digital cameras capture images with a subsampling method via mosaic color filter array (CFA). Of particular interest is the CFA with Cyan-Magenta-Yellow (CMY) color filters. Despite the improvement of the sensitivity, images reconstructed from CMY CFA usually suffer from lower color fidelity compared to the conventional Red-Green-Blue (RGB) color filters. In this paper, we proposed a CMY CFA with novel spectral sensitivities (CMY2.0), which were carefully designed to overcome the shortcomings of previous CMY CFA (CMY1.0). A CMY CMOS image sensor (CIS) with such optimized spectral sensitivities is then realized in order to evaluate the color performance and signal-to-noise ratio (SNR). As a result, the camera equipped with the CMY CFA with proposed spectral sensitivities (CMY2.0) features both an improved sensitivity and a high color fidelity, which is suitable for a wide range of applications, such as low-light photography, under-screen cameras and automotive cameras.

Implementation of an Isolated I2C Interface Device Based on OOK Codec

As a wide used protocol in industry, BMS and T&D system, I2C bus with isolation features stands out to provide additional safety protection and noise immunity. This paper introduces an implementation method of the isolated I2C interface device with high reliability and low delay. This device can meet the I2C ultra-high speed working mode with communication frequency of 1.7MHz as well as prevent the occurrence of interlock in bi-directional communication. The device is fabricated in 0.18um CMOS process.

Frequency Compensation Network for Three-Stage CMOS Operational Amplifier

The rapid advancements of CMOS integrated circuits technologies lead designers to cascade structures and avoiding cascode amplifiers. As a result, frequency compensation becomes the most important issue since multi-stage amplifiers are highly potential to instability. Here in this work, two differential stages are exploited to form frequency compensation network. These stages realize four Miller loops and share each Miller capacitor in two loops simultaneously. This intensifies Miller effect to improve frequency response due to pole-zero cancellation. The proposed three stage amplifier is modeled symbolically via a transfer function (TF) while 0.18um CMOS technology is used for circuit simulation. Good agreement between theoretical calculation and simulation results shows validity and accuracy of the TF. Also ample simulations are performed to exhibit the proposed amplifier performance against parameters mismatches. The proposed three stage amplifier expresses 105 dB as DC-gain, 4.8 MHz as Gain Band Width and 72 degree as Phase Margin. The amplifier consumes 360 uW as power consumption. This performance obviously is an improvement of Nested Miller Compensation (NMC) while Figure of Merits (FoMs) are enhunced.

A configurable area-efficient LCoS chip design with centrosymmetric pixel array

Liquid Crystal on Silicon (LCOS) is a microdisplay technology that combines CMOS tech with integrated circuit design and liquid crystal technology. In this paper, the proposed LCOS backplane can greatly reduce size of the pixel pitch. In order to reduce the size of the pixel pitch, a digital pixel driver scheme and a new layout design are shown. The proposed LCOS with digital pixel driver scheme was fabricated using 0.18 um CMOS process technology and the simulation image have shown the correct results. The pixel size is 3 um× 6 um in this design and the area of pixel array with the resolution of 1632 × 1632 is 10127 um × 5060 um.

A CMOS down-conversion mixer for microwave radar application

This paper introduces a CMOS down-conversion mixer for microwave radar application. The mixer is based on the classical Gilbert cell architecture, using PMOS current bleeding technology and cross-coupling as a transconductance stage to further elevate the conversion gain and decrease the noise factor, while introducing source negative feedback technology to enhance the linearity performance of the mixer. Using the SMIC 0.13 um CMOS process, the simulation results prove that the frequency conversion gain of the mixer is 12.31 dB, the noise factor is 21.16 dB, and the -1dB compression point of the output is -12.66 dBm when the input RF signal is 10 GHz and the output IF signal is 10 MHz. The third-order intermodulation cut-off point is -1.70 dBm, and the power dissipation is 3.16 mW under a 1.2 V power supply.

Implementation of 2-bit Multiplier Circuit Using Pass Transistor Logic

Abstract: In this paper, we implemented 2-bit Multiplier Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The proposed Multiplier circuit is implemented in 2x2 bit multiplier to achieve high speed, low area and less power dissipation. VLSI schematic tool and the analysis is done by using the LT Spice simulator. This paper aims at an optimization of power area and voltages of multiplier to show the better performance. The design is implemented in 0.18um CMOS technology and its functional parameters are compared and the best result is incorporated. Simulation results have been performed on LT Spice tool simulator at 1.8v and 2v supply voltage and simulations are carried out indicate the functionality of the proposed multiplier circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

New resistor-less tunable floating and grounded FDNR simulators

ABSTRACT This article proposes new electronically tunable simulation configurations of synthetic grounded and floating frequency-dependent negative resistances (FDNRs) without using any resistances. The presented simulators have been realised by using two voltage differencing transconductance amplifiers (VDTAs) along with two capacitances. As per the knowledge of the authors, the depicted VDTA-based simulator circuits are the most compact configurations as compared to any other VDTA-based pure FDNR simulator reported so far. The circuits possess the feature of electronic tunability which means that the realised FDNR value can be controlled by using bias currents of employed VDTAs. Moreover, the reported structures simulate ideal FDNR behaviour without any requirement of fulfiling the parameter-related conditions. An analysis has been presented and discussed to find the behaviour of the presented circuits under non-ideal effects. The operation of the simulated FDNRs has been checked by constructing higher-order CDR filters. The working of the designed circuits has been shown through the simulation results generated using PSPICE with 0.18 um CMOS technology. Finally, the experimental results using commercial IC have been discussed.

A Low Power Fully Differential Level-Crossing ADC With Low Power Charge Redistribution Input for Biomedical Applications

A low-power fully differential level-crossing analog-to-digital converter (LC-ADC) for biomedical applications is presented. Different from conventional ADCs based on the uniform sampling rate, LC-ADC generates fewer samples for biomedical signals and leads to less power consumption in the following blocks. In this design, the power consumption of n-bit DAC and digital parts is reduced significantly with respect to the conventional LC-ADCs. The proposed method uses a charge redistribution block (CRB) instead of the n-bit DAC, which leads to a large reduction in average switching energy. Besides energy-saving, the proposed switching scheme also reduces the complexity of the controlling logic circuit, providing reduced complexity and low power consumption. Another advantage of the proposed LC-ADC is its fully differential structure. As a result, SNDR is improved by decreasing the levels of even harmonics. The proposed LC-ADC is designed in 0.18 um CMOS technology. Post-layout simulation results show an effective number of bits (ENOB) of up to 6.8 bits with about 97-188 nW power consumption under 0.8 V supply voltage and input signal bandwidth from 1 Hz to 4 kHz. The ADC occupies a silicon area of only 60×65 μm2.

The study and analysis of using CMY color filter arrays for 0.8 um CMOS image sensors

Digital color cameras detect scenes through color filter array (CFA) of mosaic patterns. Among existing filter arrays in commercial CMOS image sensors (CIS), the CMY color filter set is one that is a more desirable choice for low-illuminating conditions. However, these color filters generally suffered from lower color fidelity than their counterpart RGB color filters. Nevertheless, the overall CIS performance were affected not only by the pigments used for color filters but also by the detailed structure designs and CFA arrangement of the pixel itself, we tends to explore the best combination for both the color filter materials and the pixel designs that will improve CIS performance for low light conditions that will have applications in astrophotography, low phototoxicity bioimaging, as well as general photography during dawn and dusk.

Correlated Double Amplifying Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer

MEMS capacitive accelerometer for the Internet of things applications is designed with open-loop structure rather than close-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout structure instead of charge control readout structure is preferred for low cost. However, the voltage control readout structure suffers from low power efficiency (in terms of <i>FoM</i>) due to significant parasitic-capacitance-induced noise. In this paper, the correlated double amplifying (CDA) technique is proposed to reduce the noise of the voltage control readout circuit with high power efficiency. Although, traditional correlated double sampling (CDS) technique can also be used in readout circuit to reduce the parasitic-capacitance-induced noise, it sacrifices driving ability and bandwidth of the readout circuit while CDA does not. The CDA technique adopts correlated amplifying to reduced noise without significant increase of power consumption. Thus, CDA technique leads to higher power efficiency. The CDA technique is demonstrated in a fully-differential readout circuit fabricated in a 0.18um CMOS process and tested with a sensing element from a commercial MEMS accelerometer. The measurement results show that noise floor of the readout circuit is 0.5<i>aF</i>/&#x221A;<i>Hz</i> and the noise floor of the whole system is 112<i>ug</i>/&#x221A;<i>Hz</i>, with a power consumption of 139&#x03BC;W and a bandwidth of 12.5kHz. The full input range is &#x00B1;4g, a <i>FoM</i>₁ of 80<i>pJ</i> and a <i>FoM</i>₂ of 254<i>uW</i> &#x2219; <i>ug</i>/<i>Hz</i> are achieved.