Linearity Enhancement Techniques for PGA Design

Abstract

This paper presents some techniques to improve the linearity of traditional resistive feedback PGAs. By utilizing the switched op-amp in the PGA, the MOS switches in the feedback resistor array can be eliminated and thus the PGA's linearity can be improved. The PGA's linearity is further improved with an additional capacitor, which is used for pre-charging the sampling capacitor to strengthen its capability to drive the sampling capacitor without any extra power consumption. The pre-charge technique is especially suitable for the case where the PGA drives a large sampling capacitance. Implemented in SMIC 0.18 um CMOS technology, the proposed PGA can achieve a gain of 0.5 or 1 and consumes 4.68 mW at a single 5 V supply with the switched output stage enabled. When driving a 20 pF sampling capacitor at a sampling frequency of 200 kHz, the simulation results show that the proposed PGA can give a 9 dBc improvement in SFDR of the sampled signal compared to the traditional PGA design and the SFDR can reach up to 114 dBc.