Ultrathin Silicon Research Articles

High-Performance Field-Effect Sensing of Ammonia Based on High-Density and Ultrathin Silicon Nanowire Channels.

Ultrathin silicon nanowires (SiNWs), grown via a high-yield and low-cost catalytic approach, are ideal building blocks for the construction of highly sensitive field-effect transistor (FET) sensors. In this work, we demonstrate a high-density growth integration of an ultrathin SiNW array, with diameter down to DNW = 24 ± 3 nm and narrow NW-to-NW spacing of only 120 nm, fabricated via an in-plane solid-liquid-solid (IPSLS) approach. Junctionless bottom-gated SiNW FETs are successfully constructed, exhibiting a high on/off current ratio of >107 and a sharp subthreshold swing of 156 mV/dec These provide an excellent platform for realizing high-performance NH3 sensing at room temperature, with a high response of 96.9% at 25 ppm and 38.6% at 2.5 ppm, rapid response time of 7.9 s for 5% response (or 85.8 s for 50% response), and superior selectivity against common volatile organic compound gases in ambient environments. Finally, the field-effect sensing mechanism is attributed to the Schottky barrier modulation by the adsorbed NH3 molecules at the metal/SiNW interface, as confirmed through an epoxy-masked selective region comparative analysis. These results provide a solid basis for the ultrathin catalytic IPSLS-SiNWs to serve as advantageous one-dimensional (1D) channels for the scalable integration of various high-performance and flexible gas sensing applications.

Characterization results of MAPS digital prototypes for the ALICE ITS3

The three innermost layers of the ALICE Inner Tracking System (ITS2) will be replaced by a truly cylindrical tracker, the ITS3, to be ready for LHC Run 4 (2029-2032). The ITS3 will be composed of three layers, each made by two self-supporting, ultra-thin (≤50μm) flexible Monolithic Active Pixel silicon Sensors (MAPS) of large area (O(10 × 26 cm2)). The final sensor will be realized using the 65 nm CMOS imaging process and stitching technology. Multiple small-scale test structures were included in the first production run (Multiple Layer Reticle 1 - MLR1) to validate the 65 nm CMOS imaging technology. First large-scale stitched MAPS were included in the second production run (Engineering Run 1 - ER1). The pixel cell performance has been qualified on the MLR1 Digital Pixel Test Structures (DPTS) in laboratory and with in-beam measurements. The large-area (1.4 × 25.9 cm2) ER1 MOnolithic Stitched Sensor (MOSS) prototype has been used to prove the stitching principle and evaluate the detection efficiency and spatial resolution. This contribution will give an overview of the most recent results of the digital prototype tests.

Design and fabrication of ultrathin silicon-based strain gauges for piezoresistive pressure sensor

Ultra-thin (20 μm) silicon strain gauges were fabricated with silicon-on-insulator (SOI) wafer by a newly-conceived wet etching process. Buffered oxide etchant (BOE, NH4F: HF = 6:1) solution with additives of octylamine and octanol was used for wet etching process in which the operating temperature was 50°C. Photoresist as a passivation layer was deposited on the upper side of SOI wafer to minimize strain gauge damage by chemical etchants. Small amount of octylamine and octanol were added to BOE solution to improve surface wettability and SiO2/Si selectivity. The fabricated strain gauges were attached to the pressure diaphragm and the performance of strain gauge was investigated by measuring with the hydraulic pressure system. The resistance changed linearly with tensile and compressive strains. Maximum values of non-linearity, hysteresis, thermal coefficient of resistance (TCR) and sensitivity were -0.341 %, 0.909 %, 4128 ppm/°C and 34.22 mV/V respectively. The fabricated strain gauges might be well applicable to the hydrogen pressure sensor which is detectable for high pressure range (0–900 bar).

Modelling of insulating potential in ultra-thin (42 å) silicon oxide film

Based on previously conducted measurements of the tunneling current-voltage characteristics of metal-SiO2-Si (MOS) structures, modeling of the insulating potential in an ultra-thin (4.2 nm) silicon oxide film was performed. The potential in the dielectric was defined in the shape of a trapezoid, with the lateral slopes simulating transition layers and the top base representing the bulk of SiO2. The model parameters – the barrier height and the coordinates of the trapezoid's corner points – were calculated to achieve the maximum match between the experimental and theoretical voltage derivatives of the current logarithm. Common features of the insulating potential, similar to those in thinner silicon oxide films (3.7 nm), were identified: the barrier occupies up to half of the nominal volume of the dielectric gap and is shifted towards the gate electrode, with its slope towards the semiconductor substrate being much more gradual compared to the slope adjacent to the gate.

Study on Microstructure and Texture of Fe-3%Si Ultra-Thin Ribbons Prepared by Planar Flow Casting.

In this paper, Fe-3%Si ultra-thin ribbons prepared by the planar flow casting (PFC) technique were subjected to temper rolling and annealing treatments. The microstructure and texture evolution during this process were examined through experimental measurements coupled with crystal plasticity finite element (CPFE) simulation to assess the feasibility of preparing ultra-thin non-oriented silicon steel using PFC ribbons. The results indicate that the PFC ribbons exhibit a significant columnar crystal structure, and {001}-oriented grains comprise over 30%. After being annealed, the grains with different orientations grew uniformly, the texture components were basically unchanged, and the {001} texture was well preserved. When annealing was carried out after temper rolling with a reduction rate of 7%, uneven grain growth was observed, and the growth tendency of the {001} grains, especially, surpassed that of the {111} grains, with an elevated temperature which peaked at 950 °C, where the proportion of {001} grains was maximal. When being annealed after temper rolling to 15%, grains of other orientations showed significant growth at each temperature, while the {001} grains did not show an obvious growth advantage. Utilizing the CPFE, the deformation-stored energy distribution of each characteristic-oriented grain was simulated, and it was shown that compared to the 15% rolling reduction rate, the deformation-stored energy accumulation of {001}-oriented grains after being rolled to 7% reduction was significantly lower than that of {111}-oriented grains. It suggests that the larger stored energy difference makes {001} grains show a stronger growth advantage based on the SIBM mechanism during annealing, after being rolled with a reduction rate of 7%. Overall, for the synergistic optimization of microstructure and texture, rolling with a 7% reduction rate followed by annealing at 950 °C in a hydrogen atmosphere is most advantageous.

Rapid Assessment of Biomarkers on Single Extracellular Vesicles Using "Catch and Display" on Ultrathin Nanoporous Silicon Nitride Membranes.

Extracellular vesicles (EVs) are particles released from cells that facilitate intercellular communication and have tremendous diagnostic and therapeutic potential. Bulk assays lack the sensitivity to detect rare EV subsets relevant to disease, and while single EV analysis techniques remedy this, they are often undermined by complicated detection schemes and prohibitive instrumentation. To address these issues, a microfluidic technique for EV characterization called "catch and display for liquid biopsy (CAD-LB)" is proposed. In this method, minimally processed samples are pipette-injected and fluorescently labeled EVs are captured in the nanopores of an ultrathin membrane. This enables the rapid assessment of EV number and biomarker colocalization by light microscopy. Here, nanoparticles are used to define the accuracy and dynamic range for counting and colocalization. The same assessments are then made for purified EVs and for unpurified EVs in plasma. Biomarker detection is validated using CD9 and Western blot analysis to confirm that CAD-LB accurately reports relative protein expression levels. Using unprocessed conditioned media,CAD-LB captures the known increase in EV-associated ICAM-1 following endothelial cell cytokine stimulation. Finally, to demonstrate CAD-LB's clinical potential, EV biomarkers indicative of immunotherapy responsiveness are successfully detected in the plasma of bladder cancer patients treated with immune checkpoint blockade.

Ultrathin SiONC passivation of c-Si by UHV thermal annealing in O₂/N₂: Chemical composition, morphology, and photoluminescence insights

This study investigates the impact of Ultra-High Vacuum (UHV) Thermal annealing in a N₂/O₂ atmosphere on the passivation of Ar ion etched crystalline silicon (c-Si) surfaces. A comprehensive analysis of the resulting ultrathin Silicon OxyNitride Carbide layer (SiONC) was conducted using X-ray Photoelectron Spectroscopy (XPS), Ultra-Violet Spectroscopy (UPS), Photoluminescence Spectroscopy (PL), and Atomic Force Microscopy (AFM). XPS revealed a significant transformation in chemical composition from a carbon-rich contaminated surface SiO1.02C2.98 to an oxygen- and nitrogen-containing passivated layer SiO0.13N0.10C0.28. UPS measurements elucidated changes in the electronic structure and Fermi level position at the c-Si/SiONC interface. AFM imaging demonstrated the formation of non-uniform SiONC islands, influencing surface morphology. Notably, PL spectroscopy indicated enhanced orange and red luminescence with energies of 2.0 and 1.73 eV, respectively, attributed to the SiONC layer. The enhanced luminescence, coupled with improved thermal stability and oxidation resistance, positions the SiONC layer as a promising material for advancing the performance of silicon-based optoelectronic devices, such as solar cells and light-emitting diodes (LEDs). This study provides fundamental insights into the correlation between the chemical, electronic, and morphological properties of the SiONC layer and its potential for improving c-Si device performance.

High-density integration of uniform sub-22 nm silicon nanowires for transparent thin film transistors on glass

Ultrathin catalytical silicon nanowires (SiNWs), grown as orderly arrays upon glass substrates, are ideal 1D channels for the construction of high-performance field effect transistors for low-power and high aperture/transparency electronics. In this work, a rather uniform growth integration of high-density ultrathin SiNWs has been accomplished directly on glass substrate at 290 °C, via an in-plane solid–liquid-solid mechanism. The indium (In) catalyst thickness deposited on the dense guiding terrace steps was identified as a key parameter to suppress the size dispersion of the In droplets, and thus enable a uniform growth of ultrathin SiNWs with diameters down to DNW=21.8 ± 1.8 nm, a close-to-unity guided growth rate and an excellent transparency > 90 % in spectrum ranging from 350 nm to 950 nm. Based on a convenient dry plasma etching and low-temperature passivation procedure, high-performance SiNW transistors have been successfully fabricated upon a dense array of parallel SiNWs as channels with a narrow NW-to-NW spacing of 100 nm. A high current ratio Ion/Ioff > 107, a low off-state current down to 0.1 pA, a steep subthreshold swing of SS∼120 mV dec-1 and excellent positive and negative bias stabilities have been demonstrated, as well as SiNW-based inverter logics that achieve a gain of 14.6 V/V under a drive voltage of 2.25 V. These results highlight the potential of catalytic SiNWs to serve as advantageous 1D channels for large-area display or transparent electronics.

Enhanced Corrosion Protection of Printed Circuit Board Electronics using Cold Atmospheric Plasma-Assisted SiOx Coatings.

The miniaturization and widespread deployment of electronic devices across diverse environments have heightened their vulnerability to corrosion, particularly affecting copper traces within printed circuit boards (PCBs). Conventional protective methods, such as conformal coatings, face challenges including the necessity for a critical thickness to ensure effective barrier properties and the requirement for multiple steps of drying and curing to eliminate solvent entrapment within polymer coatings. This study investigates cold atmospheric plasma (CAP) as an innovative technique for directly depositing ultrathin silicon oxide (SiOx) coatings onto copper surfaces to enhance corrosion protection in PCBs. A systematic investigation was undertaken to examine how the scanning speed of the CAP deposition head impacts the film quality and corrosion resistance. The research aims to determine the optimal scanning speed of the CAP deposition head that achieves complete surface coverage while promoting effective cross-linking and minimizing unreacted precursor entrapment, resulting in superior electrical barrier and mechanical properties. The CAP coating process demonstrated the capability of depositing SiOx onto copper surfaces at various thicknesses ranging from 70 to 1110 nm through a single deposition process by simply adjusting the scanning speed of the plasma head (5-75 mm/s). Evaluation of material corrosion barrier characteristics revealed that scanning speeds of 45 mm/s of the plasma deposition head provided an effective coating thickness of 140 nm, exhibiting superior corrosion resistance (30-fold) compared to that of uncoated copper. As a proof of concept, the efficacy of CAP-deposited SiOx coatings was demonstrated by protecting an LED circuit in saltwater and by coating printed circuits for potential agricultural sensor applications. These CAP-deposited coatings offer performance comparable to or superior to traditional conformal polymeric coatings. This research presents CAP-deposited SiOx coatings as a promising approach for effective and scalable corrosion protection in miniaturized electronics.

Lateral Electronic Junction of a Single Ultrathin Silicon Induced by Interfacial Dipole of Self-Assembled Monolayer.

Interface engineering is pivotal for enhancing the performance and stability of devices with layered structures, including solar cells, electronic devices, and electrochemical systems. Incorporating the interfacial dipole between the bulk layers effectively modulates the energy level difference at the interface and does not significantly influence adjacent layers overall. However, interfaces can drastically affect adjoining layers in ultrathin devices, which are essential for next-generation electronics with high integrity, excellent performance, and low power consumption. In particular, the interfacial effect is pronounced in ultrathin semiconductors, which have a weak electric field screening effect. Herein, the substantial interfacial impact on the ultrathin silicon is shown, the p- to n-type inversion of the semiconductor solely through the deposition of a self-assembled monolayer (SAM) without external bias. The effects of SAMs with different interfacial dipoles are investigated by using Hall measurement and surface analytic techniques, such as UPS, XPS, and KPFM. Furthermore, the lateral electronic junction of the ultrathin silicon is engineered by the regioselective deposition of SAMs with opposite dipoles, and the device exhibits rectification behavior. When the interfacial dipole of SAM is manipulated, the rectification ratio changes sensitively, and thus the fabricated diode shows potential to be developed as a sensing platform.

Magnetic Property Measurement of Ultra-Thin Silicon Steel With an Improved B–H Sensor

Magnetic Property Measurement of Ultra-Thin Silicon Steel With an Improved <i>B</i>–<i>H</i> Sensor

Research on the energy transmission mode of a three-port DC–DC converter based on ultra-thin silicon steel

With the introduction of China’s “Carbon Peaking Action Plan Before 2030,” the transformation of the power industry has released huge opportunities and potential. The DC distribution network can well-coordinate the contradiction between distributed power and grid access, fully develop the benefits of distributed energy, and become a new direction for the development of the power industry. However, the current traditional DC–DC converters have problems such as single-topology structure and low power density, which can only complete one-way transmission of energy; hence, the distributed energy cannot be fully utilized. Addressing the problem of distributed energy transfer, this paper is based on a three-port DC–DC converter for a low-voltage DC distribution network to realize energy transfer between the DC distribution network, distributed energy, and low-voltage load. First, the energy transfer modes of the three-port DC–DC converter are introduced. Combined with the converter topology and energy transfer mode, a simplified equivalent model of the converter is established. The voltage gain characteristics and frequency characteristics of this converter are studied. Furthermore, the effects of the excitation inductance to primary resonance inductance ratio parameter k and quality factor Q on the voltage gain characteristics of the converter are discussed. On this basis, the resonant cavity design of the converter is based on the optimal selection of parameters k and Q so that the converter can meet the voltage gain requirements in both forward and reverse operations. The simulation results under different loads verify the reasonableness of the resonant cavity component selection.

Low breakdown voltage and CMOS compatible avalanche photodiode based on SOI substrate.

In this work, we present a novel, to the best of our knowledge, lateral avalanche photodiode (APD) with low breakdown voltage and high bandwidth which has the potential to serve as a core device in future large-scale advanced optoelectronic hybrid chips. By taking advantage of a silicon-on-insulator (SOI) substrate combined with a separation absorption multiplier (SAM) structure, the demonstrated APDs exhibit a high gain of 148. Furthermore, the minimum breakdown voltage of the measured device is 6.1 V, which represents the lowest breakdown voltage for Si-APD, making it compatible with the existing CMOS technology for low voltage operation. Benefiting from an ultra-thin top silicon and lateral SAM structure, the problem of edge breakdown has been completely solved. Additionally, a set of device arrays with absorption and avalanche regions of different sizes is also manufactured and compared. Our findings indicate that the proposed APD has fascinating application prospects in the CMOS process-based LIDAR chips.

Iron Loss Analysis of High-Speed AFPM Motor With Ultra-Thin Silicon Steel Considering Bending Stress

Iron Loss Analysis of High-Speed AFPM Motor With Ultra-Thin Silicon Steel Considering Bending Stress

Upright Pyramid Surface Textures for Light Trapping and MoOx Layer in Ultrathin Crystalline Silicon Solar Cells

In this work, ray tracing is used to investigate the optical characteristics of various surface structures in ultrathin crystalline silicon (c-Si) for solar cells. Ultrathin c-Si with a thickness of 20 μm is used as the substrate. The light trapping includes front upright pyramids with a molybdenum oxides (MoOx) anti-reflection (AR) layer. Planar ultrathin c-Si (without a MoOx AR layer and upright pyramids) is used as a reference. The wafer ray tracer was developed by a photovoltaic (PV) lighthouse to model the MoOx AR layer to reduce the front surface reflectance and impacts of the AR layer on ultrathin Si solar cells. The optical properties are calculated on the AM1.5 global solar energy spectrum across the 200–1200 nm wavelength region. From the absorbance profile, the photogenerated current density (Jph) in the substrate is also calculated with various surface structures. The front upright pyramids with the MoOx layer result in the largest absorbance enhancement due to the enhanced light scattering by the pyramids and MoOx AR layer. The Jph of 37.41 mA/cm2 is improved when compared to the planar ultrathin c-Si reference. This study is significant as it illustrates the potential of ultrathin c-Si as a promising PV module technology in the future.

Density Functional Investigation of [001] and [111] SiNWs and the Effect of Doping with Boron and Phosphorus

In the present study, we investigate the influence of boron (B) and phosphorus (P) (p- and n-type, respectively) doping on the electronic properties of ultra-thin silicon nanowires (SiNWs) by gradient-corrected density functional calculations with the Perdew–Burke–Ernzerhof (PBE) approximation. In the limit of very small diameters (5–8 Å), both pristine and highly active unsaturated SiNWs with orientations along the [001] and [111] directions exhibit electronic states around the Fermi level, indicative of conductive properties. Conduction is further enhanced by the introduction of doping atoms, as demonstrated by the relative change in the band structures of SiNWs with and without B and P doping. This investigation provides an important insight into the electronic states of SiNWs, which are candidates for future electronics or sensing applications.

2D Fractal Arrays of Ultrathin Silicon Nanowires as Cost‐Effective and High‐Performance Substrate for Supercapacitors

Silicon is the most diffused material in the industry; thus, considering its high capacity for energy storage, silicon‐based materials are well studied as battery anodes and supercapacitors. Si nanowires (NWs) emerge due to the high surface to volume ratio, its compatibility with a wafer processing typical of microelectronics, and are studied as anodes for lithium batteries as well as coupled with other materials for supercapacitor application. In this article, the synthesis and application are reported as a lithium anode of 2D fractal arrays of ultrathin Si NWs obtained by a thin‐film metal‐assisted chemical etching (MACE). These Si NWs exhibit a density of about 1012 NWs cm−2, maximizing the surface to volume ratio compared to silver‐salts MACE and other NW fabrication approaches. By using 2.7 μm long NWs, a pseudo‐capacitor behavior with a specific capacitance of about 274.2 μF cm−2 at a scan rate of 50 mV s−1 is obtained. This specific capacitance is two orders of magnitude higher than the one obtained in the same condition by using NWs synthesized by silver‐salt MACE. In this result, the route is opened toward the application of these fractal arrays of ultrathin Si NWs as substrate for supercapacitors with improved efficiency.

Effects of Initial Grain Orientation and Annealing Parameters on Grain Size, Texture, and Magnetic Properties of Ultra-Thin Grain-Oriented Silicon Steel

Effects of Initial Grain Orientation and Annealing Parameters on Grain Size, Texture, and Magnetic Properties of Ultra-Thin Grain-Oriented Silicon Steel

Free-standing ultrathin silicon wafers and solar cells through edges reinforcement

Crystalline silicon solar cells with regular rigidity characteristics dominate the photovoltaic market, while lightweight and flexible thin crystalline silicon solar cells with significant market potential have not yet been widely developed. This is mainly caused by the brittleness of silicon wafers and the lack of a solution that can well address the high breakage rate during thin solar cells fabrication. Here, we present a thin silicon with reinforced ring (TSRR) structure, which is successfully used to prepare free-standing 4.7-μm 4-inch silicon wafers. Experiments and simulations of mechanical properties for both TSRR and conventional thin silicon structures confirm the supporting role of reinforced ring, which can share stress throughout the solar cell preparation and thus suppressing breakage rate. Furthermore, with the help of TSRR structure, an efficiency of 20.33% (certified 20.05%) is achieved on 28-μm silicon solar cell with a breakage rate of ~0%. Combining the simulations of optoelectrical properties for TSRR solar cell, the results indicate high efficiency can be realized by TSRR structure with a suitable width of the ring. Finally, we prepare 50 ~ 60-μm textured 182 × 182 mm2 TSRR wafers and perform key manufacturing processes, confirming the industrial compatibility of the TSRR method.

Influence of Photonics and Plasmonics Effect on Ultrathin Amorphous Silicon Thin Film Solar Cell

Abstract Our recent surge in silicon derived materials has major demand in thin film photovoltaic (PV) modules and enhancing the significant numbers. The rigorous coupled wave analysis method is a simple and fast method also known as developed to determine the light absorption and cell efficiency. The optics of thin film solar cells (amorphous silicon) garnering crucial role in the photovoltaic market. In this work, an ultrathin thin film amorphous silicon solar cell PV performance investigated by periodically textured surfaces at the nanoscale level. This analysis of periodic textured substrate was deriving optimal surface textures. The nanogratings lead to light scattering mechanism with the higher order diffraction angle and enhanced the light absorption of the incidence spectrum. The influence of grating period and height, the collection of the charge carriers increased at various wavelengths from ultraviolet, visible and infrared spectral regions are discussed with the assistance of photonic and plasmonic modes. Finally, nanoscale engineering mechanism the optimized thin film amorphous silicon solar cell yielded the highest current densities (22.6 and 23.8 mA/cm2) in both polarization modes.