Ultrathin Gate Dielectrics Research Articles

Ultrathin quasi-2D amorphous carbon dielectric prepared from solution precursor for nanoelectronics

Materials keeping thickness in atomic scale but extending primarily in lateral dimensions offer properties attractive for many emerging applications. However, compared to crystalline counterparts, synthesis of atomically thin films in the highly disordered amorphous form, which avoids nonuniformity and defects associated with grain boundaries, is challenging due to their metastable nature. Here we present a scalable and solution-based strategy to prepare large-area, freestanding quasi-2D amorphous carbon nanomembranes with predominant sp2 bonding and thickness down to 1–2 atomic layers, from coal-derived carbon dots as precursors. These atomically thin amorphous carbon films are mechanically strong with modulus of 400 ± 100 GPa and demonstrate robust dielectric properties with high dielectric strength above 20 MV cm−1 and low leakage current density below 10−4 A cm−2 through a scaled thickness of three-atomic layers. They can be implemented as solution-deposited ultrathin gate dielectrics in transistors or ion-transport media in memristors, enabling exceptional device performance and spatiotemporal uniformity.

Random telegraph noise in nanometer-scale CMOS transistors exposed to ionizing radiation

Nanometer-scale transistors often exhibit random telegraph noise (RTN) with high device-to-device variability. Recent experiments up to Grad total ionizing dose (TID) demonstrate stable RTN in planar bulk-Si metal-oxide-semiconductor (MOS) transistors and in Si fin field-effect transistors (FinFETs). In these cases, pre-existing defects in the ultrathin gate dielectrics dominate the device low-frequency 1/f noise (LFN). In contrast, III–V MOS devices with lower quality oxide/semiconductor interfaces show significant increases in LFN at much lower doses, due to the TID-induced activation of high densities of border traps. Aggressively scaled devices fabricated in Si gate-all-around nano-wire FET technology exhibit prominent defects leading to LFN and RTN. Increases or decreases of LFN in these devices during irradiation and annealing results primarily from the activation or passivation of border traps and interface traps.

Ultra-thin gate insulator of atomic-layer-deposited AlO x and HfO x for amorphous InGaZnO thin-film transistors

To strengthen the downscaling potential of top-gate amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), the ultra-thin gate insulator (GI) was comparatively implemented using the atomic-layer-deposited (ALD) AlO x and HfO x . Both kinds of high-k GIs exhibit good insulating properties even with the physical thickness thinning to 4 nm. Compared to the amorphous indium-gallium-zinc oxide (a-IGZO) TFTs with 4 nm AlO x GI, the 4 nm HfO x enables a larger GI capacitance, while the HfO x -gated TFT suffers higher gate leakage current and poorer subthreshold slope, respectively originating from the inherently small band offset and the highly defective interface between a-IGZO and HfO x . Such imperfect a-IGZO/HfO x interface further causes noticeable positive bias stress instability. Both ALD AlO x and HfO x were found to react with the underneath a-IGZO channel to generate the interface defects, such as metal interstitials and oxygen vacancies, while the ALD process of HfO x gives rise to a more severe reduction of a-IGZO. Moreover, when such a defective interface is covered by the top gate, it cannot be readily restored using the conventional oxidizing post-treatments and thus desires the reduction-resistant pre-treatments of AOSs.

A Monolayer MoS2 FET with an EOT of 1.1nm Achieved by the Direct Formation of a High-κ Er2 O3 Insulator Through Thermal Evaporation.

Achieving the direct growth of an ultrathin gate insulator with high uniformity and high quality on monolayer transition metal dichalcogenides (TMDCs) remains a challenge due to the chemically inert surface of TMDCs. Although the main solution for this challenge is utilizing buffer layers before oxide is deposited on the atomic layer, this method drastically degrades the total capacitance of the gate stack. In this work, weconstructed a novel direct high-κ Er2 O3 deposition system based on thermal evaporation in a differential-pressure-type chamber. A uniform Er2 O3 layer with an equivalent oxide thickness of 1.1nm wasachieved as the gate insulator for top-gated MoS2 field-effect transistors (FETs). The top gate Er2 O3 insulator without the buffer layer on MoS2 exhibited a high dielectric constant that reached 18.0, which is comparable to that of bulk Er2 O3 and is the highest among thin insulators (< 10nm) on TMDCs to date. Furthermore, the Er2 O3 /MoS2 interface (Dit ≈ 6 × 1011 cm-2 eV-1 ) is confirmed to be clean and is comparable with that of the h-BN/MoS2 heterostructure. These results prove that high-quality dielectric properties with retained interface quality can be achieved by this novel deposition technique, facilitating the future development of 2D electronics.

Miniaturized pH‐Sensitive Field‐Effect Capacitors with Ultrathin Ta2O5 Films Prepared by Atomic Layer Deposition

Miniaturized electrolyte–insulator–semiconductor capacitors (EISCAPs) with ultrathin gate insulators have been studied in terms of their pH‐sensitive sensor characteristics: three different EISCAP systems consisting of Al–p‐Si–Ta2O5(5 nm), Al–p‐Si–Si3N4(1 or 2 nm)–Ta2O5 (5 nm), and Al–p‐Si–SiO2(3.6 nm)–Ta2O5(5 nm) layer structures are characterized in buffer solution with different pH values by means of capacitance–voltage and constant capacitance method. The SiO2 and Si3N4 gate insulators are deposited by rapid thermal oxidation and rapid thermal nitridation, respectively, whereas the Ta2O5 film is prepared by atomic layer deposition. All EISCAP systems have a clear pH response, favoring the stacked gate insulators SiO2–Ta2O5 when considering the overall sensor characteristics, while the Si3N4(1 nm)–Ta2O5 stack delivers the largest accumulation capacitance (due to the lower equivalent oxide thickness) and a higher steepness in the slope of the capacitance–voltage curve among the studied stacked gate insulator systems.

Heterogeneous Functional Dielectric Patterns for Charge-Carrier Modulation in Ultraflexible Organic Integrated Circuits.

Flexible electronics have gained considerable attention for application in wearable devices. Organic transistors are potential candidates to develop flexible integrated circuits (ICs). A primary technique for maximizing their reliability, gain, and operation speed is the modulation of charge-carrier behavior in the respective transistors fabricated on the same substrate. In this work, heterogeneous functional dielectric patterns (HFDP) of ultrathin polymer gate dielectrics of poly((±)endo,exo-bicyclo[2.2.1]hept-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) are introduced. The HFDP that are obtained via the photo-Fries rearrangement by ultraviolet radiation in the homogeneous PNDPE provide a functional area for charge-carrier modulation. This leads to programmable threshold voltage control over a wide range (-1.5 to +0.2V) in the transistors with a high patterning resolution, at 2V operational voltage. The transistors also exhibit high operational stability over 140 days and under the bias-stress duration of 1800s. With the HFDP, the performance metrics of ICs, for example, the noise margin and gain of the zero-VGS load inverters and the oscillation frequency of ring oscillators are improved to 80%, 1200, and 2.5kHz, respectively, which are the highest among the previously reported zero-VGS -based organic circuits. The HFDP can be applied to much complex and ultraflexible ICs.

基于超薄Al2O3栅绝缘层的低工作电压IGZO薄膜晶体管及其在共源极放大器中的应用

基于超薄Al2O3栅绝缘层的低工作电压IGZO薄膜晶体管及其在共源极放大器中的应用

Uniform and ultrathin high-κ gate dielectrics for two-dimensional electronic devices

Two-dimensional semiconductors could be used as a channel material in low-power transistors, but the deposition of high-quality, ultrathin high-κ dielectrics on such materials has proved challenging. In particular, atomic layer deposition typically leads to non-uniform nucleation and island formation, creating a porous dielectric layer that suffers from current leakage, particularly when the equivalent oxide thickness is small. Here, we report the atomic layer deposition of high-κ gate dielectrics on two-dimensional semiconductors using a monolayer molecular crystal as a seeding layer. The approach can be used to grow dielectrics with an equivalent oxide thickness of 1 nm on graphene, molybdenum disulfide (MoS2) and tungsten diselenide (WSe2). Compared with dielectrics created using established methods, our dielectrics exhibit a reduced roughness, density of interface states and leakage current, as well as an improved breakdown field. With the technique, we fabricate graphene radio-frequency transistors that operate at 60 GHz, and MoS2 and WSe2 complementary metal–oxide–semiconductor transistors with a supply voltage of 0.8 V and subthreshold swing down to 60 mV dec−1. We also create MoS2 transistors with a channel length of 20 nm, which exhibit an on/off ratio of over 107. Using a monolayer molecular crystal as a seeding layer, hafnium oxide dielectrics with an equivalent oxide thickness of only 1 nm can be deposited on graphene, molybdenum disulfide and tungsten diselenide.

Low-voltage organic thin-film transistors based on [n]phenacenes

Abstract Low-voltage p-channel organic thin-film transistors based on [n]phenacene (n = 5, 6 or 7) were fabricated on glass and on flexible poly(ethylene 2,6-naphthalate) (PEN) substrates. For the first time, these phenacenes were combined with two ultrathin gate dielectrics based on aluminium oxide and a monolayer of octadecyl-phosphonic acid in three different transistor structures. Regardless of the substrate and the transistor structure, the field-effect mobility is found to increase with increasing length of the conjugated [n]phenacene core, leading to the best performance for [7]phenacene. The largest average field-effect mobility we have obtained is 0.27 cm2/V⋅s for transistors on glass and 0.092 cm2/V⋅s for transistors on flexible PEN.

High‐Performance and Radiation‐Hard Carbon Nanotube Complementary Static Random‐Access Memory

AbstractSignificant progress on carbon‐nanotube (CNT) electronics means that they are a serious candidate for use in high‐performance integrated circuits (ICs). However, few works have focused on fabricating and exploring CNT complementary metal–oxide‐semiconductor (CMOS) static random‐access memory (SRAM), which is an integral part of most digital ICs. High‐performance complementary top‐gated field‐effect transistors (FETs) are fabricated through a doping‐free technology based on solution‐derived CNT films and are used in SRAM cells with a high yield and high uniformity. CNT CMOS‐architecture 6‐transistor (6‐T) SRAM exhibits read/write margins as high as ≈0.4 V with a supply voltage of 1.0 V and stable dynamic properties. Furthermore, the effects of radiation the CNT CMOS FETs and SRAM ICs are explored. Owing to the robust CC bonds in the CNTs, the ultrathin gate insulator layer in the devices, and a lack of a requirement for an isolation region, CNT FETs and SRAM cells can withstand a 2.2 Mrad total ionizing dose (TID) with a high rate of 560 rad s−1, indicating that they could be used as radiation‐hard ICs for applications in hostile environments. TID hardness of CNT‐based SRAM ICs is reported for the first time, and a dose of 2.2 Mrad is the highest measured radiation dose for CNT FETs and ICs.

Ultrathin calcium fluoride insulators for two-dimensional field-effect transistors

Two-dimensional semiconductors could be used to fabricate ultimately scaled field-effect transistors and more-than-Moore nanoelectronic devices. However, these targets cannot be reached without appropriate gate insulators that are scalable to the nanometre range. Typically used oxides such as SiO2, Al2O3 and HfO2 are, however, amorphous when scaled, and 2D hexagonal boron nitride exhibits excessive gate leakage currents. Here, we show that epitaxial calcium fluoride (CaF2), which can form a quasi van der Waals interface with 2D semiconductors, can serve as an ultrathin gate insulator for 2D devices. We fabricate scalable bilayer MoS2 field-effect transistors with a crystalline CaF2 insulator of ~2 nm thickness, which corresponds to an equivalent oxide thickness of less than 1 nm. Our devices exhibit low leakage currents and competitive device performance characteristics, including subthreshold swings down to 90 mV dec−1, on/off current ratios up to 107 and a small hysteresis. High-performance MoS2 transistors can be created using 2-nm-thick CaF2 as a gate insulator, which forms a quasi van der Waals interface with the 2D semiconductor.

Growth of graphene with large single-crystal domains by Ni foam-assisted structure and its high-gain field-effect transistors.

High-quality graphene materials and high-performance graphene transistors have attracted much attention in recent years. To obtain high-performance graphene transistors, large single-crystal graphene is needed. The synthesis of large-domain-sized single-crystal graphene requires low nucleation density; this can lead to a lower growth rate. In this study, a Ni-foam assisted structure was developed to control the nucleation density and growth rate of graphene by tuning the flow dynamics. Lower nucleation density and high growth rate (∼50 μm min−1) were achieved with a 4 mm-gap Ni foam. With the graphene transistor fabrication process, a pre-deposited Au film as the protective layer was used during the graphene transfer. Graphene transistors showed good current saturation with drain differential conductance as low as 0.04 S mm−1 in the strong saturation region. For the devices with gate length of 2 μm, the intrinsic cut-off frequency fT and maximum oscillation frequency fmax were 8.4 and 16.3 GHz, respectively, with fmax/fT = 1.9 and power gain of up to 6.4 dB at 1 GHz. The electron velocity saturation induced by the surface optical phonons of SiO2 substrates was analyzed. Electron velocity saturation and ultra-thin Al2O3 gate dielectrics were thought to be the reasons for the good current saturation and high power gain of the graphene transistors.

Monolayer Molybdenum Disulfide Transistors with Single-Atom-Thick Gates.

Two-dimensional transition-metal dichalcogenides (TMDs) are unique candidates for the development of next-generation electronic devices. However, the large contact resistance between metal and the monolayer TMDs have significantly limited the devices' performance. Also, the integration of ultrathin high- k dielectric layers with TMDs remains difficult due to the lack of dangling bonds on the surface of TMDs. We present monolayer molybdenum disulfide field-effect transistors with bottom local gates consisting of monolayer graphene. The atomic-level thickness and surface roughness of graphene facilitate the growth of high-quality ultrathin HfO2 and suppress gate leakage. Strong displacement fields above 8 V/nm can be applied using a single graphene gate to electrostatically dope the MoS2, which reduces the contact resistances between Ni and monolayer MoS2 to 2.3 kΩ·μm at low gate voltages. The devices exhibit excellent switching characteristics including a near-ideal subthreshold slope of 64 millivolts per decade, low threshold voltage (∼0.5 V), high channel conductance (>100 μS/μm), and low hysteresis. Scaled devices with 50 and 14 nm channels as well as ultrathin (5 nm) gate dielectrics show effective immunity to short-channel effects. The device fabricated on flexible polymeric substrate also exhibits high performance and has a fully transparent channel region that is desirable in optical-related studies and practical applications.

Flexible, Low-Power Thin-Film Transistors Made of Vapor-Phase Synthesized High-k, Ultrathin Polymer Gate Dielectrics.

A series of high-k, ultrathin copolymer gate dielectrics were synthesized from 2-cyanoethyl acrylate (CEA) and di(ethylene glycol) divinyl ether (DEGDVE) monomers by a free radical polymerization via a one-step, vapor-phase, initiated chemical vapor deposition (iCVD) method. The chemical composition of the copolymers was systematically optimized by tuning the input ratio of the vaporized CEA and DEGDVE monomers to achieve a high dielectric constant (k) as well as excellent dielectric strength. Interestingly, DEGDVE was nonhomopolymerizable but it was able to form a copolymer with other kinds of monomers. Utilizing this interesting property of the DEGDVE cross-linker, the dielectric constant of the copolymer film could be maximized with minimum incorporation of the cross-linker moiety. To our knowledge, this is the first report on the synthesis of a cyanide-containing polymer in the vapor phase, where a high-purity polymer film with a maximized dielectric constant was achieved. The dielectric film with the optimized composition showed a dielectric constant greater than 6 and extremely low leakage current densities (<3 × 10-8 A/cm2 in the range of ±2 MV/cm), with a thickness of only 20 nm, which is an outstanding thickness for down-scalable cyanide polymer dielectrics. With this high-k dielectric layer, organic thin-film transistors (OTFTs) and oxide TFTs were fabricated, which showed hysteresis-free transfer characteristics with an operating voltage of less than 3 V. Furthermore, the flexible OTFTs retained their low gate leakage current and ideal TFT characteristics even under 2% applied tensile strain, which makes them some of the most flexible OTFTs reported to date. We believe that these ultrathin, high-k organic dielectric films with excellent mechanical flexibility will play a crucial role in future soft electronics.

Two-Port-Network-Based Method to Measure Electrical Characteristics of MIS Devices With Ultrathin Barriers

MISFETs with ultrathin gate insulator layers are often used as switches in highly integrated circuits. For such transistors, gate currents can be problematic. For devices with nonnegligible channel resistance, such as oxide FETs, gate leakage currents also cause difficulties in measuring the devices’ capacitance–voltage ( CV ) characteristics. Here, we present a method to measure CV characteristics of MIS devices that is also applicable to devices with sizable channel resistances and large leakage currents.

(Dielectric Science and Technology Division Thomas D. Callinan Award Address) Dielectrics for MOS Integrated Circuits

Introduction Insulator films are one of the fundamental elements of the semiconductor integrated circuits together with semiconductor substrate/films and metal/silicide interconnects. Functions of the insulator films in ICs (Integrated Circuits) are roughly classified into the following 6 categories; a) isolation between active devices, b) gate insulator of MOSFETs/MOS capacitors/MIM (Metal Insulator Metal) capacitors, c) sidewall insulation films for gate electrode, d) interlayer isolation films for interconnects, e) passivation films above the interconnects to cover and protect the IC chip surface, and f) insulator film between surface Si layer and Si substrate in SOI (Silicon On Insulator) wafer. In this paper, author’s past works related to the insulator films used ICs are reviewed. Introduction of BPSG reflow technique into NMOS LSI technology One of the severe problems for ICs until the middle of 1970’s was the disconnection of the aluminum interconnects at the steps of insulation film over the edges of poly Si lines and field SiO2 regions. The author applied BPSG (BoroPhospho Silicate Glass) reflow technique for the first time in the world to his developed NMOS LSI technologies in Toshiba, making the steps completely smooth, verifying the yield, and long term reliability in the 1k bit SRAM products in 1975. Finding of plasma induced damage to the gate oxide during ion-implantation and reactive ion etching The author developed a 64k bit DRAM technology from late 1970’s to the beginning of 1980’s. The introduction of source/drain heavy ion-implantation and RIE (Reactive Ion Etching) techniques of poly Si gate electrodes (2nd poly Si) were necessary to fabricate the designed small cell size. The accumulated ionic charge to the capacitor poly electrodes (1st poly Si) during the ion-implantation and reactive ion etching broke the 3 nm gate oxide of the 1st poly Si capacitor, causing bit errors of DRAM. This phenomena were published at the late news of ECS for the first time in the world in 1982 (1). Introduction of RTN gate oxide to prevent the boron penetration In early 1990’s CMOS technology changed from that of single n+-poly Si gate to dual poly Si gate (n+-poly Si for NMOSFETs and p+-poly Si for PMOSFETs) technology, in order to suppress the short-channel effect of PMOSFETs. Because the boron diffusion through the gate SiO2 during the high temperature thermal process is very large, the high-concentration boron penetration from the p+-poly Si to the PMOSFET channel through the gate SiO2 became a big problem. This was known to be solved by introduction of nitrogen to the SiO2. The author and his colleagues demonstrated that the RTN (Rapid Thermally Nitrided) SiO2 gate film completely suppress the boron penetration even the nitrogen concentration in SiO2 is only several percent, for the first time in 1990 (2). Introduction of direct-tunneling gate oxide for CMOS logic device It has been assumed that the gate oxide thinning limit would be 3 nm, because of the significant increase of the gate leakage current by direct-tunneling mechanism. However, the author and his colleagues demonstrated that MOSFETs with 1.5 nm thick direct-tunneling gate oxide operate quite normally, even though there is the direct-tunneling leakage, when decreasing the gate length less than 0.1 um, because the ratio between the gate leakage current and the drain current deceases in proportion to the square of the gate length reduction rate (3). Demonstration of the 0.4 nm EOT La-silicate gate oxide MOSFETs In order to decrease the gate length of MOSFETs to 5 nm, EOT (Equivalent Oxide Thickness) of the gate oxide should be 0.4 nm. The author and his colleagues developed La-silicate high-k metal gate technology and demonstrated the excellent operation of 0.4 nm EOT MOSFETs (4). Reference S. Sawada, S. Maeda, Y. Matsumoto, H. Iwai, H. Nihira, and O. Ozawa, “Degradation of thin gate oxide under process induced electrical stress”, 162nd ECS Fall Meeting, Recent Newspapers, Detroit, USA, October, (1982).T. Morimoto, H. S. Momose, K. Yamabe, and H. Iwai, “Prevention of boron penetration from p+ poly gate by RTP produced thin gate oxide”, ESSDERC 90, Nottingham, England, September, (1990), 73.H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, H. Iwai, “Tunneling gate oxide approach to ultra-high current drive in small-geometry MOSFETs”, in IEDM Tech. Dig., December, (1994), 593H. Iwai, T. Yasuda et al., “Research and development for second generation of ultra-thin gate insulator material”, NEDO Forum 2012 on energy saving technology, Tokyo, November, (2012): in Japanese

Use of self-assembled monolayers for selective metal removal and ultrathin gate dielectrics in MoS2 field-effect transistors

We demonstrate a simple and rapid method for the fabrication of multilayer molybdenum disulfide (MoS2) field-effect transistors (FETs) by exploiting various functions of an octadecylphosphonic acid (ODPA)-based self-assembled monolayer (SAM). The SAM is used both for selective metal removal in patterning to simplify the fabrication process and as an ultrathin gate dielectrics in the device. The low voltage operation of the MoS2 FETs was observed with a low gate leakage current and small hysteresis. In addition, selective metal removal can effectively narrow the spacing between the gate and contact electrodes, resulting in improved device characteristics. This approach also makes it possible to transfer thinner and smaller MoS2 flakes. This study suggests intriguing applications of the SAM for the fabrication of functional electronic devices.

Chemical vapor deposition of monolayer MoS2 directly on ultrathin Al2O3 for low-power electronics

Monolayer MoS2 has recently been identified as a promising material for high-performance electronics. However, monolayer MoS2 must be integrated with ultrathin high-κ gate dielectrics in order to realize practical low-power devices. In this letter, we report the chemical vapor deposition (CVD) of monolayer MoS2 directly on 20 nm thick Al2O3 grown by atomic layer deposition (ALD). The quality of the resulting MoS2 is characterized by a comprehensive set of microscopic and spectroscopic techniques. Furthermore, a low-temperature (200 °C) Al2O3 ALD process is developed that maintains dielectric integrity following the high-temperature CVD of MoS2 (800 °C). Field-effect transistors (FETs) derived from these MoS2/Al2O3 stacks show minimal hysteresis with a sub-threshold swing as low as ∼220 mV/decade, threshold voltages of ∼2 V, and current ION/IOFF ratio as high as ∼104, where IOFF is defined as the current at zero gate voltage as is customary for determining power consumption in complementary logic circuits. The system presented here concurrently optimizes multiple low-power electronics figures of merit while providing a transfer-free method of integrating monolayer MoS2 with ultrathin high-κ dielectrics, thus enabling a scalable pathway for enhancement-mode FETs for low-power applications.

Automatic Parameter Extraction Technique for MOS Structures by C-V Characterization Including the Effects of Interface States

Abstract An automatic MOS structure parameter extraction algorithm accounting for quantum effects has been developed and applied in the semiconductor device analyzer Agilent B1500A. Parameter extraction is based on matching the experimental C-V data with numerical modeling results. The algorithm is used to extract the parameters of test MOS structures with ultrathin gate dielectrics. The applicability of the algorithm for the determination of distribution function of DOS and finding the donor defect level in silicon is shown.

Self-Assembled Monolayer-Based Gate Dielectrics for MoS2 FETs

In this study, self-assembled monolayer (SAM)-based gate dielectrics is applied to the fabrication of molybdenum disulfide (MoS2) field-effect transistors (FETs). A fabrication process of MoS2 FETs involves the selective formation of a SAM on aluminum oxides and the manual transfer of MoS2 flakes. A subthreshold slope (SS) of 69 mV/dec and no hysteresis were attained with the ultrathin SAM-based gate dielectrics. These results indicate the superior interfacial properties of the MoS2/SAM structure. Cross-sectional transmission electron microscopy revealed a flat and abrupt interface of the MoS2/SAM structure. It is found that the SAM-based gate dielectrics is applicable to the fabrication of low-voltage MoS2 FETs. This study opens up intriguing possibilities of SAM-based gate dielectrics in functional electronic devices.