Ultrathin Channel Layer Research Articles

Preparation of High Performance Metal Oxide Synaptic Transistor with Ultra-thin Channel Layer

Preparation of High Performance Metal Oxide Synaptic Transistor with Ultra-thin Channel Layer

Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model

The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field was evaluated. The TFET was fabricated by inserting an epitaxially-grown parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer.

Back Gate Bias Stressing on Extremely Thin SOI (ETSOI) MOSFETs with Gate Last Process Integration

In this paper, ETSOI transistors fabricated with gate last process scheme with thin channel layers of 4 to 11nm are provided with superior device performance. For a given gate length less than 30nm, DIBL and Swing are achieved with 48mV/V and 65mV/Dec respectively with stressing of back gate bias. Threshold voltage can be tuned within range of 0.8 volts (Vdd=-0.05v). It is large enough for adjusting device performance. Back gate bias stressing would enhance carrier confinement to top gate while large electrical field is induced in the ultra-thin channel layer which would impact on the performance of DIBL. Also, from our results, it is shown that device with thicker channel layer of 11nm are more sensitive to back gate bias comparing with that with thinner channel layer of 4nm.

Comparison Study of Metal Induced Lateral Crystallized and Solid-Phase Crystallized Polycrystalline Silicon Thin Film Transistors with Different Channel Thickness

N- and P-type polycrystalline silicon thin film transistors are fabricated with channel thickness of 30 nm and 100 nm by metal induced lateral crystallization (MILC) and conventional solid-phase crystallization (SPC) of amorphous silicon. Significant improvement is obtained for the MILC devices by ultrathin channel layer. But for SPC devices, improvement is not as significant. The possible reasons are proposed and discussed.