Ultrathin Buffer Layer Research Articles

Enhanced contact resistance reduction in MoS2 transistors via ultrathin LiPON electrode interface doping

Two-dimensional (2D) semiconductors are considered one of the most promising channel materials in devices for the future development of integrated circuits with low power consumption and high integration. As the size of the device gradually decreases, a key challenge is to reduce the contact resistance of nanoscale devices. Doping is a crucial strategy to realize low contact resistances in 2D devices, but there is still lack of simple and compatible doping methods. Here, we report a simple and localized doping strategy that adopts an ultrathin lithium phosphorus oxynitride (LiPON) as the buffer layer of electrodes to reduce the contact resistance of MoS2 transistors. This ultrathin buffer layer induces strong n-doping in the electrode contact area, thereby achieving nearly Ohmic contact in the devices. The contact resistances of LiPON/Ti/Au electrodes for different channel carrier densities are all lower than those of Ti/Au electrodes because the Schottky barrier height (SBH) for the LiPON/Ti/Au electrodes is only 8% of the value for the Ti/Au electrodes. This work provides a simple and compatible strategy for the development of high-performance 2D devices and deepens the understanding of the important role of doping in 2D electrical contacts.

Achieving low-voltage operating high-mobility organic thin-film transistors by a multi-layered gate dielectric

Organic thin-film transistors (OTFTs) have attracted great attention for their inherent advantages and promising applications in emerging fields. Simultaneously realizing low-voltage operation and high-mobility in one OTFT is one of prerequisites for the commercialization, which is a huge challenge so far. An important route to address this challenge is to develop an ideal gate dielectric with a high capacitance and a low interfacial trap density at the dielectric/channel. In this Letter, we demonstrate the low-voltage operating high-mobility OTFTs by elaborately designing and processing a multi-layered gate dielectric. The gate dielectric consists of a high permittivity polymer film, a polymer buffing layer with a high surface energy, and an ultrathin long-chain alkane buffer layer. The effects of both the structures and the processes of gate dielectrics on the performances of OTFTs are investigated in detail. In addition, the relevant physical mechanisms are discussed. Finally, the optimal OTFTs exhibit high mobilities with the average and maximum values up to 5.62 and 6.74 cm2/V s, respectively, at low operating voltages below −5 V. Our findings reveal that designing and processing a reasonable multi-layered gate dielectric is a promising strategy to achieve both high-mobility and low-voltage operation in OTFTs, thereby fostering their development.

Controlled Fabrication of Composite Transparent Electrodes for Semitransparent Perovskite Solar Cells with above 84% Fill Factor

In the quest to develop efficient semitransparent perovskite solar cells (ST‐PSCs), the primary challenge lies in transparent electrode fabrication. n–i–p‐type ST‐PSCs often suffer from low fill factors (FF) and power conversion efficiency (PCE), attributed to the undesirable buffer layer/transparent conductive oxide combination of the transparent electrode. In this context, this study proposes an efficient composite transparent electrode (CTE) system comprising an ultrathin MoO3 buffer layer (5 nm) and low‐power sputtered indium zinc oxide (45 W–220 nm). The electrode demonstrates excellent compatibility with Spiro‐OMeTAD‐based devices, effectively addressing the low FF and PCE challenges of ST‐PSCs. Employing the new CTE, the best‐performing ST‐PSCs with the absorption edge at 1.57 eV achieve a remarkable PCE of 21.96% with an FF of up to 83.80%. More transparent ST‐PSCs with thickness‐modulated absorbers and average transmittance of 50.77% at 600–1200 nm wavelength result in a PCE of up to 20.91% with the highest known FF of 84.02%. This study presents a general and viable approach for fabricating efficient ST‐PSCs.

Epitaxial growth of high-quality GaAs on Si(001) using ultrathin buffer layers

The direct growth of III–V semiconductors on silicon holds tremendous potential for photonics applications. However, the inherent differences in their properties lead to defects in the epitaxial layer, including threading dislocations (TDs), antiphase boundaries (APBs), and thermal cracks, significantly impacting device performance. Current processes struggle to suppress these defects simultaneously, necessitating the development of methods to inhibit TDs and APBs in a thin buffer on silicon. This study introduces a GaSb buffer layer during GaAs epitaxy on a silicon (001) substrate. This approach successfully suppresses defect formation by promoting the formation of interfacial misfit dislocation arrays at both the AlSb/Si and GaAs/GaSb interfaces. The resulting GaAs layer exhibits a step-flow surface with a rough mean square of ∼3.8 nm and a full width at half maximum of 158 arcsec. Remarkably, the growth is achieved without any observable interfacial intermixing. Building on this platform, InAs/GaAs quantum dots are grown with a density of 3.8 × 1010 cm−2, emitting at a wavelength of 1288 nm. This breakthrough holds immense promise for developing high-quality GaAs films with reduced defect densities on silicon for O band lasers, laying the foundation for the mass production of silicon-based integrated circuits.

Improvement of high energy X-ray optical performance of W/Si supermirror by optimizing interface compounds using ultra-thin buffer layer

The high energy spectral properties of X-ray supermirrors are governed mainly by the interface diffusion and compound formation at the interfaces. Using ion beam sputtering technique, a set of W/Si periodic multilayers with C buffer layer (BL) and without C BL have been prepared and the effect of BL has been studied by grazing incidence specular X-ray reflectivity, diffused X-ray scattering and X-ray photoelectron spectroscopy. Using C BL at the W-on-Si interfaces, reduction of interface diffusion and minimization of WSix formation at the interfaces has been observed though signature of carbide formation has been noticed. Using the results an interface diffusion model has been proposed explaining the effect of C BL. Block method of X-ray supermirror design has been effectively used for reducing the number of layers of W/Si supermirror targeting the improvement of the performance. Finally, 36-layer W/Si supermirror with C BL and without C BL have been fabricated and the performance evaluated by reflectivity measurement using 25 keV synchrotron X-rays and cross sectional TEM measurements. This study has both technological implication in X-ray optical devices and also offers atomistic insight into the mechanism of improvement of the interface quality by application of ultra-thin buffer layer.

Fully-vertical GaN-on-SiC Schottky barrier diode with ultrathin AlGaN buffer layer

In this letter, vertically conductive GaN epilayer on SiC substrate was achieved without the typically used conductive buffer layer. Here, in order to reduce the impacts of band offset of different layers on vertical conductivity and improve the vertical carrier transportation, an ultrathin AlGaN buffer layer was employed to replace the thick conductive buffer layer. Fully-vertical Schottky barrier diode (SBD) based on this vertically conductive epi-stack demonstrated a much lower specific on-resistance of 0.84 mΩ·cm2 with superior thermal stability. Moreover, the SBD also exhibited an on/off ratio of ∼5 × 109 and a nearly unity ideality factor of 1.08. This approach lays the foundation for the heterogeneous integration of GaN/SiC based devices.

Using a perovskite oxide buffer layer on Ca2Nb3O10 nanosheets for the epitaxial growth of Pb(Zr0.52Ti0.48)O3 for electrode-free thin films

Ca2Nb3O10 nanosheet layers were deposited on Gallium Nitride (GaN)-on-Si substrates by the Langmuir-Blodgett method to obtain (001)-oriented growth of perovskite oxide thin films using pulsed laser deposition. We investigated the influence of 10 nm thick SrTiO3, (LaAlO3)0.3(Sr2AlTaO6)0.7 (LSAT) and LaMnO3 films as buffer layers on the structural and ferroelectric properties of subsequentially grown Pb(Zr0.52Ti0.48)O3 (PZT) films, which may be used as gate capacitors in high power GaN devices. Scanning Electron Microscopy, Atomic Force Microscopy, X-Ray-Diffraction and in-plane polarization experiments were used to determine the influence of the oxide buffer layers on the PZT properties. Highly crystalline dense (001)-oriented PZT films with large in-plane polarizations were obtained using SrTiO3 and LSAT as buffer layers. For SrTiO3 and LSAT we observed an improvement of the structural and ferroelectric properties compared to PZT grown directly on the Ca2Nb3O10 nanosheets and or using a LaMnO3 buffer layer. The improved high-crystallinity PZT films grown on GaN using ultrathin buffer layers could enhance the performance of high-power semiconductor electronics or in other devices where there is a need for a ferroelectric layer without bottom electrode.

Improved Electrical Resistivity of Atomic-Layer-Deposited Copper Thin Films on Polyimide Substrates by an In Situ ZnO Interlayer.

The low-temperature atomic layer deposition of metal on polymer surfaces is often challenging owing to the deficiency of functional groups and reactivity. Here, the deposition of ALD-Cu employing Cu(hfac)2 and Et2Zn at a low temperature (120 °C) on polyimide (PI) substrates is improved by the utilization of an in situ ultrathin ALD-ZnO buffer layer. A conformal and continuous ALD-Cu thin film with low resistivity (6.07 μΩ cm) is fabricated on an ALD-ZnO/PI substrate. The findings demonstrate that the ALD-ZnO buffer layer provides chemisorption and a nucleation site for the initial growth of ALD-Cu. Transmission electron microscopy and energy-dispersive X-ray analysis reveal that the ALD-ZnO layer plays a buffer role in the fitness of ALD-Cu on PI substrates and its ability to elicit the formation of an ALD-ZnO nanocluster and polar surface. ALD-ZnO can be effectively utilized as a buffer layer for polymer-based ALD-metal processes, showing potential in flexible electronic applications.

Enhanced Switching Reliability of Hf0.5Zr0.5O2 Ferroelectric Films Induced by Interface Engineering.

Ferroelectric materials have been widely researched for applications in memory and energy storage. Among these materials and benefiting from their excellent chemical compatibility with complementary metal-oxide-semiconductor (CMOS) devices, hafnia-based ferroelectric thin films hold great promise for highly scaled semiconductor memories, including nonvolatile ferroelectric capacitors and transistors. However, variation in the switched polarization of this material during field cycling and a limited understanding of the responsible mechanisms have impeded their implementation in technology. Here, we show that ferroelectric Hf0.5Zr0.5O2 (HZO) capacitors that are nearly free of polarization "wake-up"─a gradual increase in switched polarization as a function of the number of switching cycles─can be achieved by introducing ultrathin HfO2 buffer layers at the HZO/electrodes interface. High-resolution transmission electron microscopy (HRTEM) reveals crystallite sizes substantially greater than the film thickness for the buffer layer capacitors, indicating that the presence of the buffer layers influences the crystallization of the film (e.g., a lower ratio of nucleation rate to growth rate) during postdeposition annealing. This evidently promotes the formation of a polar orthorhombic (O) phase in the as-fabricated buffer layer samples. Synchrotron X-ray diffraction (XRD) reveals the conversion of the nonpolar tetragonal (T) phase to the polar orthorhombic (O) phase during electric field cycling in the control (no buffer) devices, consistent with the polarization wake-up observed for these capacitors. The extent of T-O transformation in the nonbuffer samples is directly dependent on the duration over which the field is applied. These results provide insight into the role of the HZO/electrodes interface in the performance of hafnia-based ferroelectrics and the mechanisms driving the polarization wake-up effect.

Semitransparent Perovskite Solar Cells with Ultrathin Protective Buffer Layers.

Semitransparent perovskite solar cells (ST-PSCs) are increasingly important in a range of applications, including top cells in tandem devices and see-through photovoltaics. Transparent conductive oxides (TCOs) are commonly used as transparent electrodes, with sputtering being the preferred deposition method. However, this process can damage exposed layers, affecting the electrical performance of the devices. In this study, an indium tin oxide (ITO) deposition process that effectively suppresses sputtering damage was developed using a transition metal oxides (TMOs)-based buffer layer. An ultrathin (<10 nm) layer of evaporated vanadium oxide or molybdenum oxide was found to be effective in protecting against sputtering damage in ST-PSCs for tandem applications, as well as in thin perovskite-based devices for building-integrated photovoltaics. The identification of minimal parasitic absorption, the high work function and the analysis of oxygen vacancies denoted that the TMO layers are suitable for use in ST-PSCs. The highest fill factor (FF) achieved was 76%, and the efficiency (16.4%) was reduced by less than 10% when compared with the efficiency of gold-based PSCs. Moreover, up-scaling to 1 cm2-large area ST-PSCs with the buffer layer was successfully demonstrated with an FF of ∼70% and an efficiency of 15.7%. Comparing the two TMOs, the ST-PSC with an ultrathin V2Ox layer was slightly less efficient than that with MoOx, but its superior transmittance in the near infrared and greater light-soaking stability (a T80 of 600 h for V2Ox compared to a T80 of 12 h for MoOx) make V2Ox a promising buffer layer for preventing ITO sputtering damage in ST-PSCs.

Wafer-scale high-κ dielectrics for two-dimensional circuits via van der Waals integration

The practical application of two-dimensional (2D) semiconductors for high-performance electronics requires the integration with large-scale and high-quality dielectrics—which however have been challenging to deposit to date, owing to their dangling-bonds-free surface. Here, we report a dry dielectric integration strategy that enables the transfer of wafer-scale and high-κ dielectrics on top of 2D semiconductors. By utilizing an ultra-thin buffer layer, sub-3 nm thin Al2O3 or HfO2 dielectrics could be pre-deposited and then mechanically dry-transferred on top of MoS2 monolayers. The transferred ultra-thin dielectric film could retain wafer-scale flatness and uniformity without any cracks, demonstrating a capacitance up to 2.8 μF/cm2, equivalent oxide thickness down to 1.2 nm, and leakage currents of ~10−7 A/cm2. The fabricated top-gate MoS2 transistors showed intrinsic properties without doping effects, exhibiting on-off ratios of ~107, subthreshold swing down to 68 mV/dec, and lowest interface states of 7.6×109 cm−2 eV−1. We also show that the scalable top-gate arrays can be used to construct functional logic gates. Our study provides a feasible route towards the vdW integration of high-κ dielectric films using an industry-compatible ALD process with well-controlled thickness, uniformity and scalability.

High-performance solid-state lithium metal batteries achieved by interface modification

Garnet-structured ceramic electrolyte Li6.75La3Zr1.75Ta0.25O12 (LLZTO) attracts significant consideration in solid-state Li metal batteries due to its wide electrochemical window and favorable compatibility with Li metal. However, the deployment of LLZTO is severely hampered by poor contact between LLZTO and Li metal anode. In this paper, an ultra-thin Al-Si interface buffer layer (10 nm) is constructed on LLZTO by a magnetron sputtering method, which allows superior wetting of Li onto the LLZTO surface due to the alloying reaction between the Al-Si layer and Li metal. The resulting Li/Al-Si coated LLZTO (ASL)/Li symmetrical cell delivers an interfacial resistance of 15.0 Ω cm−2, which is much lower than that of 1140.3 Ω cm−2 for the bare LLZTO symmetrical cell. Moreover, the Li/ASL/Li symmetrical cells exhibit stable plating/striping performance (800 h) with small voltage hysteresis at 1.0 mA cm−2. Besides, the full cell with LiFePO4 cathode reveals a high capacity of 124.1 mA h g−1 after 600 cycles at 0.5C with a low-capacity decay of 0.032% per cycle. We believe this work will facilitate the development of solid-state rechargeable batteries.

Boost the Efficiency of Cu2ZnSn(S,Se)4 Solar Cell by Using Mn2+‐Induced Ultrathin CdS Buffer Layer

In this article, the efficiency of CZTSSe solar cell is improved by adding manganese chloride in the deposition solution of the CdS buffer layer. The mechanisms behind the experimental results are investigated. On one hand, the MnCl2 can facilitate the deposition of an ultrathin (≈10 nm) CdS buffer layer. The decreased thickness of the buffer layer can reduce the parasitic absorption loss of the solar cell. As the result, the short‐circuit current density of the solar cell is increased. On the other hand, the Mn2+ in the deposition solution can diffuse into the CZTSSe layer during the deposition of the buffer layer. The incorporation of Mn in CZTSSe would decrease the acceptor level of CZTSSe, reduce the defects at the CZTSSe/CdS interface, and increase the activation energy for the main recombination path in CZTSSe solar cell. These can lead to the reduction of the carrier recombination in the depletion region of the solar cell. As the result, the open‐circuit voltage of CZTSSe solar cell is improved. By using the ultrathin CdS buffer layers, the efficiency of CZTSSe solar cell is improved from 10.0% to 12.0% (active area efficiency).

Influence of an ultra-thin buffer layer on the growth and properties of pseudomorphic GaAsBi layers

A series of 100 nm-thick pseudomorphic GaAsBi layers with the Bi content varying from 0.97 to 11.2% have been grown by molecular beam epitaxy (MBE) on the semi-insulating GaAs(100) substrates buffered with an ultra-thin up to 20 nm thick GaAs layer. The main attention in this work was focused on the investigation of relaxation in the Bi induced compressively-strained GaAsBi layers containing a various content of Bi. The lattice parameters of GaAs- Bi compound and the Bi concentration have been evaluated from high resolution X-ray diffraction measurements. The relaxation values of GaAsBi layers ranging from 0.4 to 3.5% were obtained analyzing the symmetric and asymmetric reciprocal space maps of (004) and (115) planes, respectively. Also, the complex study was performed to clarify the relaxation effect on structural, morphological and optical properties of bismide layers. Optical measurements revealed a significant reduction of the energy band gap from 1.34 to 0.92 eV for the layers containing 0.97–8.6% of Bi in the GaAs lattice.

Ultrathin SnO2 Buffer Layer Aids in Interface and Band Engineering for Sb2(S,Se)3 Solar Cells with over 8% Efficiency

The environmentally friendly antimony selenosulfide (Sb2(S,Se)3) semiconductor emerges as a promising light harvester for thin-film photovoltaics owing to its excellent material and optoelectronic properties. The alloyed Sb2(S,Se)3 is endowed with the complementary benefits of Sb2S3 and Sb2Se3, such as a tunable band gap within the range of 1.10–1.70 eV. In Sb2(S,Se)3 solar cells, the n-type semiconductor CdS is extensively used as an electron transport layer (ETL), which plays a role in extracting photogenerated electrons from absorbers and transporting them to conducting substrates. However, the unsatisfactory ETL/absorber interface contact often involves severe interface recombination. Herein, we report that an ultrathin SnO2 buffer layer of ∼10 nm applied on the high-roughness fluorine-doped tin oxide (FTO) substrate aids in effective interface and band engineering for superstrate CdS/Sb2(S,Se)3 solar cells. Careful characterizations confirm that the ultrathin SnO2 buffer layer plays a positive role in inhibiting the shunt current leakage at the ETL/absorber interface and manipulating the cascade energy band structure for more effective interface passivation and efficient electron extraction. Consequently, the resultant SnO2/CdS ETL-based Sb2(S,Se)3 solar cells exhibited a remarkable device efficiency of 8.67%, coupled with a considerable open-circuit voltage of 0.72 V. Our finding demonstrates a facile approach to engineer the interface contact and band offset to accelerate electron extraction, transport, and collection efficiencies.

Interfacial engineering for semi-insulating GaN/sapphire template with low dislocation density

Achieving semi-insulating (SI) GaN epilayers with low threading dislocation density (TDD) on sapphire substrates is critically important but challenging for electronic and optoelectronic devices. To obtain low-TDD SI GaN within a thin layer, herein, we performed interfacial engineering for early regulating dislocation and impurity behaviors. It is found that introducing an ultrathin (10 nm) sputtered AlN interfacial buffer layer can effectively suppress dislocations and oxygen (O) impurities. Compared with GaN and thick AlN buffer layers, the ultrathin AlN buffer layer can be nano-pixelated into discrete islands with higher density, ensuring an adequate three-dimensional growth with locally quick coalescence. Hence, the TDD value of the GaN epilayer was rapidly decreased to a low level at the earlier stage of growth. In addition, benefiting from the high diffusion barrier of O in AlN, AlN buffers demonstrate a superior blocking effect of O impurities over GaN buffer, even if the thickness is only 10 nm. Finally, GaN epilayer with a TDD value of 2.7 × 108 cm−2 and a sheet resistance of 2.43 × 1011 Ω/sq can be achieved at the same time. The interfacial buffer engineering provides a simple and effective strategy to obtain high-crystalline-quality SI materials, without additional negative effects introduced.

Self-assembled HfO2-Au nanocomposites with ultra-fine vertically aligned Au nanopillars.

Oxide-metal-based hybrid materials have gained great research interest in recent years owing to their potential for multifunctionality, property coupling, and tunability. Specifically, oxide-metal hybrid materials in a vertically aligned nanocomposite (VAN) form could produce pronounced anisotropic physical properties, e.g., hyperbolic optical properties. Herein, self-assembled HfO2-Au nanocomposites with ultra-fine vertically aligned Au nanopillars (as fine as 3 nm in diameter) embedded in a HfO2 matrix were fabricated using a one-step self-assembly process. The film crystallinity and pillar uniformity can be obviously improved by adding an ultra-thin TiN-Au buffer layer during the growth. The HfO2-Au hybrid VAN films show an obvious plasmonic resonance at 480 nm, which is much lower than the typical plasmonic resonance wavelength of Au nanostructures, and is attributed to the well-aligned ultra-fine Au nanopillars. Coupled with the broad hyperbolic dispersion ranging from 1050 nm to 1800 nm in wavelength, and unique dielectric HfO2, this nanoscale hybrid plasmonic metamaterial presents strong potential for the design of future integrated optical and electronic switching devices.

High-performance a-IGZO-based flexible TTFT with stacked dielectric layers via ultrathin high-κ SrTiO3 buffer layer grown on HfO2

High-performance a-IGZO-based flexible TTFT with stacked dielectric layers via ultrathin high-κ SrTiO3 buffer layer grown on HfO2

Improved Efficiency for Silicon‐Based Perovskite Light‐Emitting Diodes via Interfacial Hydrophilic Modification

AbstractSilicon‐based perovskite light emitting diodes (PeLEDs) possess great potential in the fields of silicon‐based display devices and on‐chip light sources. However, the contact problem between metal electrodes and solution‐processed hole/electron transport layers generally deteriorates the device performance. Here, an interfacial hydrophilic modification strategy is proposed to solve the contact issue between the metal electrode and the hole transport layer poly(3,4‐ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) in Si‐based PeLEDs. By introducing an ultrathin NiOx buffer layer on the hydrophobic Au bottom electrode, the morphology of the PEDOT:PSS layer as well as the luminescence properties of the quasi‐2D perovskite layer spin‐coated on top of it are able to be dramatically improved. As a result, the optimized Si‐based PeLEDs reach a maximum external quantum efficiency of 4.46% with a current efficiency of 19.7 cd A−1, which is the highest value for Si‐based quasi‐2D PeLEDs to the authors’ knowledge.

Band-offset reduction for effective hole carrier collection in bifacial silicon heterojunction solar cells

Bifacial silicon heterojunction (SHJ) solar cells are gaining popularity owing to their potential for high performance. To achieve bifacial illumination, wide-gap hydrogenated nanocrystalline silicon oxide (nc-SiOx:H) materials are used as front and rear surface fields, which significantly enhance the light absorbed into the cells. In this study, we reduced the band offset at the p/i interface of bifacial SHJ solar cells using an ultra-thin buffer layer of hydrogenated amorphous silicon oxide (a-SiOx:H) to increase the efficiency of hole carrier transport and collection. Effectively, we were able to enhance the open-circuit voltage (Voc) and fill factor (FF) by 0.97% and 9.59%, respectively. These results were confirmed through experimental procedures and simulations. Subsequently, the experimental efficiency with respect to the bifacial illumination of a rear emitter silicon heterojunction solar cell was increased by 23.6%, with a Voc of 729 mV, FF of 80%, and short-circuit current density of 40.5 mA/cm2.