Ultra Small Form Factor Research Articles

Understanding the Impact of Environmental Conditions on Zero-Power Internet of Things: An Experimental Evaluation

The booming Internet of Things is transforming all industries, making them more productive and efficient. Unfortunately, with its widespread use, a series of challenges are posed by sustainable sensing, harsh working environments, laboursome battery replacement, and the requirement for an ultra-small form factor. The concept of zero-power Internet of Things has recently been proposed to overcome these challenges by integrating farfield wireless power transfer, ambient energy harvesting, and backscatter wireless communications into networked embedded systems. However, the development of far-field wireless power transfer is still in its infancy, and how environmental conditions affect its performance in the real world remains unclear. This article fills this gap and provides an extensive experimental study to quantify the impact of environmental conditions, namely, lineof- sight propagation, multipath interference, building materials, and non-air mediums on far-field wireless power transfer. Inspired by this study, we further shed light on some future research directions.

A high-T c van der Waals superconductor based photodetector with ultra-high responsivity and nanosecond relaxation time

Photodetectors based on nano-structured superconducting thin films are currently some of the most sensitive quantum sensors and are key enabling technologies in such broad areas as quantum information, quantum computation and radio-astronomy. However, their broader use is held back by the low operation temperatures which require expensive cryostats. Here, we demonstrate a high-T c superconducting photodetector, which shows orders of magnitude improved performance characteristics of any superconducting detector operated above 77 K, with a responsivity of 9.61 × 104 V W−1, theoretically achievable noise equivalent power of 15.9 fW Hz1/2 and nanosecond relaxation times. At 15 K the detector reaches an ultra-high performance of 2.33 × 107 V W−1 and 55.2 aW Hz1/2. It is based on van der Waals heterostructures of the high temperature superconductor Bi2Sr2CaCu2O8+δ , which are shaped into nano-wires with ultra-small form factor using focused helium ion beam irradiation. To highlight the versatility of the detector we demonstrate its fabrication and operation on a telecom grade SiN waveguide chip. Our detector significantly relaxes the demands of practical applications of superconducting detectors and displays its possible potential for photonics based quantum applications.

A Survey on Energy Management for Mobile and IoT Devices

Editor’s notes: Mobile and IoT devices have proliferated our daily lives. However, these miniaturized computing systems should be highly energy-efficient due to their ultrasmall form factor. Hence, energy management is of utmost importance for both mobile and IoT devices. This article presents a comprehensive survey on this topic. — Partha Pratim Pande, Washington State University

Historical Perspective of System in Package (SiP)

Moore Stress calls for technology and architecture innovation, and System in Package (SiP) is critical to address the challenge. System in Package is a generalization of System on Chip. As such, SiP is a giant chip rather than a miniaturized Printed Circuit Board (PCB). SiP using Wafer Level Package (WLP) enables performance efficient and cost effective integration of DRAM and logic. SiP with Integrated Passive Devices (IPD) provides high quality and low energy platforms for mixed signal and RF circuits. Billions of chips are shipped each year using SiP due to ultra small form factor with very low power consumption for smartphones, smart wearable devices such as smart watches, and Internet of Things (IoT).

A digitally compensated 1.5 GHz CMOS/FBAR frequency reference

A temperature-compensated 1.5 GHz film bulk acoustic wave resonator (FBAR)-based frequency reference implemented in a 0.35 microm CMOS process is presented. The ultra-small form factor (0.79 mm x 1.72 mm) and low power dissipation (515 microA with 2 V supply) of a compensated FBAR oscillator present a promising alternative for the replacement of quartz crystal frequency references. The measured post-compensation frequency drift over a 0-100 degrees C temperature range is < +/- 10 ppm. The measured oscillator phase noise is -133 dBc/Hz at 100 kHz offset from the 1.5 GHz carrier.

Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips

Power dissipation in microprocessors is projected to reach a level that may necessitate chip-level liquid cooling in the near future. An on-chip microchannel heat sink can reduce the total thermal interfaces between an integrated circuit chip and the convective cooling medium and therefore yield smaller junction-to-ambient thermal resistance. This paper reports the fabrication, assembly, and testing of a silicon chip with complementary metal-oxide-semiconductor process compatible microchannel heat sink and thermofluidic chip input/output (I/O) interconnects fabricated using wafer-level batch processing. Ultra-small form factor, low-cost fabrication and assembly (system integration) are achieved for 2D and 3D chips, as the microchannel heat sink is fabricated directly on back-side of each chip. Through-wafer electrical and fluidic vias are used to interconnect the monolithically integrated microchannel heat sink to thermofluidic chip I/O interconnections. The feasibility of the novel fluidic I/O interconnect is demonstrated through preliminary thermal resistance measurements.

Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink

Power dissipation in microprocessors will reach a level that necessitates chip-level liquid cooling in the near future. An on-chip microfluidic heat sink can reduce the thermal interfaces between an IC chip and the convective cooling medium. Through wafer-level processing, integrated thermal-fluidic I/O interconnects enable on-chip microfluidic heat sinks with ultrasmall form factor at low-cost. This letter describes wafer-level integration of microchannels at the wafer back-side with through-wafer fluidic paths and thermal-fluidic input/output interconnection for future generation gigascale integrated chips.