Ultra Large Scale Integration Research Articles

(Invited, Digital Presentation) Langmuir-Type Formulation for Atomic-Order Surface Reactions of Reactant Gases on Si (100) and Ge (100) Surfaces

Accurate knowledge of atomically controlled processing for group IV semiconductors is very important for the fabrication of Si-based ultrasmall devices in ultralarge-scale integration [1]. In this review, the Langmuir-type formulation is performed for atomic-order surface reactions of reactant gases on group IV semiconductor (100) surface in ultraclean hot-wall low-pressure CVD. Now, assuming that one reactant molecule M is adsorbed at one free surface site with partial decomposition of M, total site density n0 on the surface is given by n 0 = Q s + Q Ms, (1)where Q s is density of free site; Q Ms, the site density where M is adsorbed.Then the surface adsorption velocity of Q Ms is given bydQ Ms/dt = k Ms P M Q s - k -Ms Q Ms = k Ms P M n 0 - (k Ms P M + k -M) Q Ms, (2)where k Ms and k -Ms is adsorption and desorption rate constants of M, respectively; P M, partial pressure of M. The integration of eq. (2) with Q Ms = 0 at t =0 gives Q Ms= [k Ms P M n 0/(k Ms P M + k -Ms)]{1 - exp[ - (k Ms P M + k -Ms)t]}. (3)The self-limited adsorption given by eq. (3) with fitted n 0 and k Ms (k -Ms = 0) fits the experimental data of CH4 on Si(100) at 500-600oC [2], SiH3CH3 on Si and Ge(100) at 450oC [3], B2H6 on hydrogen(H)-free Si (100) at 180oC [4], PH3 on Ge (100) at 300oC [5], SiH4 on H-free Ge (100) at 260oC [6]. It is mentioned that H-free surface is prepared by preheating at the higher temperature than around 400oC on Si (100) and 300oC on Ge (100) in Ar and at the higher temperature the self-limited amount is scarcely influenced even by H2 in the present condition. In the case of NH3 at 400oC on H-terminated Si (100) [7] and SiH4 at 260oC on H-terminated Ge (100) [6], it is proposed that the NH3 or SiH4 molecules are physically adsorbed self-limitedly at H-terminated sites. Then, total site density n H0 is given by n H0 = Q Hs + Q MHs + Q HMR, (4)where Q Hs is the site density of H-terminated site; Q HMs, the site density where M is adsorbed physically at H-terminated site; Q HMR, the site density where physically adsorbed M at H-terminated site decomposes partially. If the relationship between Q Hs and Q HMs is Q HMs=K HM Q Hs with thermal equilibrium constant K HM, the surface decomposition velocity of Q HMR is given bydQ HMR/dt = k HMR Q HMR = k HMR K HM P M(n H0 - Q HMR), (5)where k HMR is partial decomposition rate constant of adsorbed M.The integration of Eq. (5) with Q HMR = 0 at t =0 gives Q HMR=n H0(1 - exp { - [k HMR K HM P M/(1 + K HM P M)]t}). (6)The H-terminated surface is composed of H-free and H-terminated sites. For fraction x of the H-terminated sites, total site density is n 0 (1 - x) + n H0 x and the self-limited amount is given by Q Ms (1 - x) + Q HMR x.The self-limited adsorption/reaction for NH3 at 400oC on H-terminated Si (100) surface and SiH4 at 260oC on H-terminated Ge (100) surface given by eqs. (3) and (6) with x, n 0, n H0, k Ms, K HM and k HMR fits the experimental data. For the SiH4, SiH3CH3 or PH3 where total site density on the surface is equal to substrate surface atomic density n SSA, it is assumed that the site is the pair site such as Si-Si, Si-Ge or Ge-Ge pair. For CH4, B2H6 or NH3 where the total site density is equal to 2n SSA, it is proposed that the site is one bond of Si or Ge. In the PH3 on Si (100) [5], it is assumed that P atoms of maximum 2n SSA are adsorbed with self-limited reaction rate constant of PH3 at the P occupied sites where PH3 molecules have been adsorbed at Si-Si pair sites [8]. These results demonstrate that the atomic level surface reactions of reactant gases in the practical low-pressure CVD are explained based on the modified Langmuir-type model.

Acceleration Mechanism of Triethanolamine in Electroless Bath for Pure Cobalt Deposition

The utilization of hydrazine as a reducing agent in the electroless cobalt bath is indispensable for the application of pure cobalt film fabrication in ultra-large-scale integration (ULSI). However, the deposition rate using the ordinary coating bath is relatively low. After conducting numerous experiments in this study, we have made a groundbreaking discovery: the deposition rate of electroless plating pure cobalt bath can be significantly increased from less than 1.0 μ·h−1 to more than 5.0 μ·h−1 by adding triethanolamine (TEA) as an accelerator. This remarkable finding greatly enhances the practical value of the electroless cobalt plating bath and enables its application in microholes filling of cobalt interconnect lines below 10 nm. According to the results of linear sweep voltammetry and mixed potential theory, the addition of TEA essentially forms [Co(C6H5O7)(TEA)2]2 2− complex with more feasible reductivity than that of the [Co(C6H5O7)(H2O)]2 2− in the ordinary plating bath and the cobalt center is favorable to be released under the electroless reduction attack to the unstably strong steric hindrance of TEA, which significantly increases the reduction current of Co(II) ions. After the further optimization of pH, temperature and annealing process, not only does resistivity decrease to 12.1 μΩ·cm, but also the surface morphology and crystallinity improve significantly. Therefore, an applicable electroless cobalt plating protocol with a moderate deposition rate is obtained.

Room Temperature Light Emission from Superatom-like Ge-Core/Si-Shell Quantum Dots.

We have demonstrated the high-density formation of super-atom-like Si quantum dots with Ge-core on ultrathin SiO2 with control of high-selective chemical-vapor deposition and applied them to an active layer of light-emitting diodes (LEDs). Through luminescence measurements, we have reported characteristics carrier confinement and recombination properties in the Ge-core, reflecting the type II energy band discontinuity between the Si-clad and Ge-core. Additionally, under forward bias conditions over a threshold bias for LEDs, electroluminescence becomes observable at room temperature in the near-infrared region and is attributed to radiative recombination between quantized states in the Ge-core with a deep potential well for holes caused by electron/hole simultaneous injection from the gate and substrate, respectively. The results will lead to the development of Si-based light-emitting devices that are highly compatible with Si-ultra-large-scale integration processing, which has been believed to have extreme difficulty in realizing silicon photonics.

Near infrared photoluminescence of Si1–xGex quantum dots fabricated by double hot Ge+/Si+ implantation into SiO2 layer

In this study, we developed very simple and ULSI (ultra large scale integration) compatible fabrication processes for group-IV (Si1–xGex and Si) semiconductor quantum dots (QDs) to apply hybrid ULSIs with photonic and electron devices, using double Ge+/Si+ hot-ion implantation into a SiO2 layer with larger bandgap EG and the post-furnace annealing. We successfully demonstrated the near-infrared (IR) photoluminescence (PL) from Si1–xGex-QDs. Transmission electron microscopy observations of single-crystallized Si1–xGex-QDs revealed that the diameter and the QD density were 3.6 ± 0.9 nm and (2.6 ± 0.4) × 1012 cm−2, respectively. In addition, Ge atoms were detected in the Si1–xGex-QDs by the energy dispersive x-ray spectroscopy analysis, and the Ge fraction of Si1–xGex-QDs was varied from 0.06 to 0.26 by changing the Ge ion dose. The increase in the PL intensity by forming gas annealing was attributed to the dangling-bond reduction by the H-atom termination method. The PL spectrum of Si1–xGex-QDs was fitted by PL components of two QD structures containing Si1–xGex and Si materials. The PL intensity and PL-peak photon energy of Si1–xGex-QDs strongly depended on the Ge fraction. The Si1–xGex-QDs achieved the maximum PL intensity at x ≈ 0.13. High PL-peak photon energy (∼1.31 eV) of Si1–xGex-QDs is attributed to the quantum confinement effect of carriers in QDs. Consequently, group-IV semiconductor QDs including Si1–xGex, Si, SiC, and C, through the simple hot-ion implantation into the SiO2 layer, exhibited a wide range of PL emissions from the near-IR to ultraviolet regions.

A review on effect of various high-k dielectric materials on the performance of FinFET device

The scalability of bulk CMOS faced various possible issues due to inherent material and process innovation constraints. Alternatively, transistor devices with supplementary gates, such as the Fin Field-effect transistor (FinFET) structure has attracted developing interest during the last few generations of their emergence, attributable to the appropriate control of the gate electrode over subthreshold parameters and seem to be favorable for Ultra large-scale integration, resulting in excessive immune function to short-channel effects (SCEs). In this paper, we will see the effect of several types of high-k gate dielectrics materials i.e Hafnium oxide (HfO2), Lanthanum doped zirconium oxide (LaZrO2), Silicon dioxide (SiO2), crystalline-silicon (c-Si), and polycrystalline-silicon (poly-Si), etc. channels are characterized for the short channel effects (SCEs), leakage current, Ion/Ioff ratio, drain induced barrier lowering (DIBL), and subthreshold swing (SS). The effect of important device parameters is considered regarding SCEs. The variation of the materials indicates improvements for the SCEs in FinFETs device architecture and also enhanced effective carrier mobility. Hence, we can clearly see that the use of high-k gate material has allowed for effective control of the diminishing of short channel effects.

Advancement and Challenges of Biosensing Using Field Effect Transistors.

Field-effect transistors (FETs) have become eminent electronic devices for biosensing applications owing to their high sensitivity, faster response and availability of advanced fabrication techniques for their production. The device physics of this sensor is now well understood due to the emergence of several numerical modelling and simulation papers over the years. The pace of advancement along with the knowhow of theoretical concepts proved to be highly effective in detecting deadly pathogens, especially the SARS-CoV-2 spike protein of the coronavirus with the onset of the (coronavirus disease of 2019) COVID-19 pandemic. However, the advancement in the sensing system is also accompanied by various hurdles that degrade the performance. In this review, we have explored all these challenges and how these are tackled with innovative approaches, techniques and device modifications that have also raised the detection sensitivity and specificity. The functional materials of the device are also structurally modified towards improving the surface area and minimizing power dissipation for developing miniaturized microarrays applicable in ultra large scale integration (ULSI) technology. Several theoretical models and simulations have also been carried out in this domain which have given a deeper insight on the electron transport mechanism in these devices and provided the direction for optimizing performance.

(Invited, Digital Presentation) Langmuir-Type In-Situ Doping Mechanism in Si1-xGex Epitaxial Growth by Chemical Vapor Deposition

Accurate knowledge of atomically controlled processing for group IV semiconductors is very important for the fabrication of Si-based ultrasmall metal–oxide–semiconductor (MOS) devices and Si-based heterodevices in ultralarge scale integration because high-performance devices require atomically ordered interface of heterointerfaces and doping profiles as well as strain engineering due to introduction of Ge and C into Si [1-6]. In this work, in-situ doping of dopant (P or B) and C in Si1-xGex (100) epitaxial growth using SiH4-GeH4-SiH3CH3-B2H6 or PH3- H2 gas mixtures at around 550 oC [7-9] is reviewed based on the Langmuir-type surface adsorption and reaction scheme and the experimental data.It is assumed that one SiH4 or GeH4 molecule in Si1-xGex growth is adsorbed at one free surface site in Si-Si, Si-Ge or Ge-Ge pair sites on the (100) surface and decomposes there, and that one dopant (SiH3CH3 or B2H6 or PH3) molecule occupies one free surface site, independently of SiH4 and GeH4 partial pressures.For in-situ doping of C, it is proposed that SiH3CH3 molecules are adsorbed and react at the pair sites and react at the B-occupied sites where B2H6 molecules have been adsorbed at the pair sites.For in-situ doping of B, it is proposed that B2H6 molecules are adsorbed and react at the pair sites and SiH4, GeH4, SiH3CH3 and B2H6 molecules react at the B-occupied sites.For in-situ P doping, it is proposed that both the P concentration and the Ge fraction x in Si1-xGex are enhanced by the self-limited adsorption of PH3 molecules with maximum 2 and maximum 1 atomic layers at the P-occupied sites where PH3 molecules have been adsorbed at Si-Si and Si-Ge pair sites, respectively and that the decrease of P concentration in Si1-xGex with increasing PH3 partial pressure in high P concentration region is caused by lower segregation coefficient of P at Si-Ge and Ge-Ge pair sites than that at Si-Si pair sites according to the Henry’s law.Fairly good agreement is obtained between all the experimental data and the calculated values using the modified Langmuir-type mechanism.These results open the way for generalization of atomically controlled surface reaction process in group IV semiconductors by CVD.[1] J. Murota: The Electrochemical Society Extended s, Fall Meeting, Detroit, Oct.17-21, 1982, Abs.No.226, p.363.[2] H. Ishii, Y. Takahashi and J. Murota, Appl. Phys. Lett., 47, 863 (1985).[3] J. Murota and S. Ono, Jpn. J. Appl. Phys., 33, 2290 (1994).[4] B. Tillack, B. Heinemann, D. Knoll, Thin Solid Films, 369, 189 (2000).[5] J. Murota, M. Sakuraba and B. Tillack, Jpn. J. Appl. Phys., 45, 6767 (2006).[6] B. Tillack, Y. Yamamoto, D. Bolze, B. Heinemann, H. Rücker, D. Knoll, J. Murota and W. Mehr, Thin Solid Films, 508, 279 (2006).[7] J. Murota, Y. Yamamoto, I. Costina, B. Tillack, V. Le Thanh, R. Loo and M. Caymax: ECS J. Solid State Sci. Technol., 7(6), P305 (2018).[8] J. Murota and H. Ishii, ECS J. Solid State Sci. Technol., 10(2), 024005 (2021).[9] J. Murota and H. Ishii, ECS J. Solid State Sci. Technol., 10(6), 064004 (2021).

Design, simulation and analysis of high-K gate dielectric FinField effect transistor

The devices with additional gates like Fin Field effect transistor (FinFET) provide higher control on subthreshold parameters and are favorable for Ultra large-scale integration. Also, these structures provide high control on current through the channel and with minimum leakage. In this paper we designed a FinFET with high-K gate dielectric material i.e Hafnium oxide as gate oxide. A comparison of similar sized transistor with Air and Silicon dioxide as gate material is performed. The comparison is mainly in terms of performance parameters like transconductance, subthreshold slope, and drain current characteristics. There is an increase in ON current on using a high-K dielectric material and subsequently an improvement in other parameters like subthreshold slope, transconductance and intrinsic gain.

A comprehensive comparative study of the performance of carbon‐ and copper‐based interconnects in ultra‐large‐scale integrated circuits

AbstractContinuous increase of transistor count in ultra‐large‐scale integrated (ULSI) circuits demands denser interconnection networks to guarantee normal operation. As the distances between adjacent interconnect lines shrinks, severe crosstalk effects appear. New interconnect materials and technologies are proposed to alleviate deteriorating crosstalk effects and maintain overall circuit performance at a desirable level. Carbon‐based materials including carbon nanotubes (CNTs) and graphene nanoribbons (GNRs) are among promising candidate materials to replace copper in future ULSI interconnects. In this work, carbon‐based interconnects including multiwall carbon nanotubes (MWCNTs) and multilayer graphene nanoribbons (MLGNRs), both horizontal (HMLGNRs) and vertical (VMLGNRs), are compared with traditional copper interconnects in terms of crosstalk delay and noise. Due to lower surface roughness, boron nitride (BN) is considered as substrate material for carbon‐based interconnects. To obtain more accurate and reliable results, layer number dependence of dielectric constant of BN multilayers and surface roughness dependence of the resistivity of HMLGNR interconnects are considered. The role of interconnect length, line spacing, and interlayer distance (substrate thickness) in crosstalk delay and noise of coupled carbon‐ and Cu‐based interconnect lines is investigated. It is shown that VMLGNR interconnects with perfect GNR edges exhibit the least crosstalk delay while MWCNT interconnects show far less crosstalk noise than other materials.

(Invited) The Contribution of Thin Film Technologies to the Future Challenges of a Connected Society

This paper highlights the future challenges related to the exponential development of connected objects and the Internet of Things. These challenges concern the integration of components, circuits and systems, the density of elementary components, but also the heterogeneous assembly, the data flow in communications and the energy consumption of the whole connected system. Indeed, current technologies and the amount of data transmitted currently lead to an exponential growth in energy consumption at the global level, a growth that will no longer be realistic and acceptable from 2030 onwards. To counteract this, the entire chain of integrated functions that are physically realized by microelectronic components, circuits and systems needs to be revisited. The main challenges will therefore focus on reducing the consumption of electronic functions including sensors and actuators, signal conversion and processing devices, energy collection and storage devices, display panels and short- and long-distance communications systems, and power electronics as well. Among these points, it should be noted that the number of sensors is increasing significantly, with predictions indicating that the number of sensors in the world is expected to reach 10 trillion by 2030, which corresponds to about a thousand sensors per inhabitant. Moreover, a strategy will have to be adapted not to increase the flow of data transmitted over long distances to data centers and cloud storage (or equivalent), but rather to prefer the use of short-range communications, which are much less energy-intensive.This evolution involves new technological approaches including very highly integrated components and circuits (ULSI or Ultra Large Scale Integration) but also thin film technologies based on inorganic and organic materials. These technologies are becoming a priority for the development of integrated sensors, energy production and storage systems and for the realization of transducers such as electrical generation of optical signals or contact-controlled flat panel displays. Three-dimensional heterogeneous structures combining the stacking of highly integrated devices with the superposition of thin film devices are also promising for data storage, which is becoming one of the major elements of databases and data centers.Depending on the desired properties, the solutions are more based on the modification of the materials constituting the basic electronic components in order to minimize the currents in the off-state but also the on-state, on the architectures of the circuits which must limit the consumption at stand-by, on the stacking of the layers constituting the devices and finally on the heterogeneous assembly involving several technologies. This will also require adapting the skills and know-how of technicians, engineers, doctors and researchers in order to overcome the technological challenges.This paper will thus successively focus on a general presentation of the challenges related to the development of connected objects and the Internet of Things, which involve all the main functions of electronics, which have consequences on all societal domains since the vast majority of applications in rapid development use electronic components and systems. Particular attention will be paid to the energy consumption of components and circuits that induce an exponential consumption of connected objects and the Internet. The next part will focus on the different approaches envisaged and more particularly on thin-film devices. In order to complete the picture, the last part will focus on the human needs in skills and know-how by giving as an example the strategy of the French microelectronics training network carried out over the last ten years. The final objective is to take up the technological and human challenges within the framework of the French electronics sector, set up in 2019 by the French government, which aims at making a significant contribution at the international level in the development of the digital society involving the Internet of Things, artificial intelligence and industry 4.0.

The Process Challenge and Optimization of Self-Aligned Contact Etch

The self-aligned contact (SAC) is a key process in developing the next generation ultra-large scale integrated (ULSI) devices because its advantage on providing an efficient reduction of active array areas, decreasing the transistor gate features, and alignment margin improvements in photolithography (1-2). With the transistor gate feature size continuously scaled down, pattern density and aspect ratios continuously increase, conversely. It requires a robust etch process to solve the multiple issues such as hard mask (HM) loss loading between different patterns (trench, hole, etc.), HM shoulder profile, sidewall profile control (3). In this work, we examined the impact of various technologies on the extremely high aspect ratio SAC etch process, including source pulsing, bias pulsing, synchronous pulsing and the atomic layer etch (ALE) methods. Results indicate the introduction of pulsing function could significantly reduce the nitride loss while avoid the contact open. The synchronous pulsing and ALE scheme shows its superior capability on improving the trade-off between HM loss and profile control. To further improve the process margin, we also introduced a novel HM shape engineering. Finally we achieved a manufacturable SAC process without any side effect. Acknowledgments The authors gratefully acknowledge support from Shanghai Sailing Program. References Kim, J. Vac. Sci. Technol. A 23(4), 7(2005).Kim, J. Vac. Scl. Technol. B 20(5), 9(2002)H. Zheng, A study of self-aligned contact etch of NOR flash , China Semiconductor Technology International Conference (2015).

Ultralow Dielectric Constant and High Temperature Resistance Composites Based on Self-Crosslinking Polysulfone and Hollow Glass Beads

In this work, ultralow dielectric constant (ultralow-k) polysulfone (PSF) composites were prepared by adding hollow glass beads (HGB) modified with 1,3-divinyltetramethyldisiloxane (DVTM). The results indicated that the surface modification of HGB (m-HGB) effectively enhanced the interfacial compatibility between the inorganic fillers and PSF matrix. DSC and TGA measurements of the composite films were performed under a nitrogen atmosphere, and the results showed that the composite films possess high glass transition temperatures varying from 187 °C to 190 °C, and are thermally stable␣up to 445 °C. The mechanical properties of composite films with modified HGB fillers show a certain drop, but the values were still higher than 32 MPa. Furthermore, the obtained composite films show low dielectric constant, low dielectric loss, good permittivity-frequency stability and dielectric-temperature stability under 190 °C. Therefore, we shown an effective path to prepare composites with ultralow dielectric constant for use in high temperature resistant ultra large scale integration (ULSI) flexible insulation substrate field.

Foreword: Special Section on “The Reliability of Advanced Microelectronic Packaging—Part II: Structure–Property Relationships”

Modern technologies and devices ranging from smartphones, computers, cloud computing, industrial automation, automobiles, to the Internet of Things are enabled by integrated circuits (ICs) and their associated packages. The ICs have evolved from the early small-scale integration (SSI) to the later more complex very-large-scale integration (VLSI) and the subsequent ultra-large-scale integration (ULSI), in a continuous quest for improved functionality, higher performance, smaller form factors, and lower cost. The rate has generally followed Moore’s law.

Study on Uniform Plasma Generation Mechanism of Electron Cyclotron Resonance Etching Reactor

Electron cyclotron resonance (ECR) plasma sources have been used widely in ultra large-scale integration (ULSI) manufacturing processes for many years. ECR plasma sources can generate plasma stably, even at very low pressures below 0.1 Pa, and the plasma’s spatial distribution can be controlled easily using the static magnetic field distribution. Furthermore, the plasma generation region can be located away from the chamber walls, which leads to reduced plasma contamination from the walls. In addition, uniform plasmas can be generated using these sources to achieve uniform plasma processing, which is crucial for large-diameter wafers such as 300 or 450 mm wafers. However, the mechanism for generation of uniform plasma using an ECR plasma source for semiconductor manufacturing is not well understood because of the complexity of the microwave propagation in the plasma. We use a plasma simulation technique to understand the uniform plasma generation mechanism in this work. We have conducted an integrated ECR plasma simulation of an etcher used for semiconductor manufacturing that combines 1) a microwave analysis in magnetized plasma, 2) a plasma generation analysis, and 3) a plasma diffusion analysis. We obtained consistent solutions for each analysis in practical calculation times of a few minutes. Additionally, we verified the simulation results by comparison with experimental plasma density measurements. We then discussed the uniform plasma generation mechanism in the ECR plasma source using simulated results for the microwave distribution in the etching reactor.

Foreword: Special Section on “The Reliability of Advanced Microelectronic Packaging—Part I: Management of Thermal Effects”

Modern technologies and devices ranging from smartphones, computers, cloud computing, industrial automation, and automobiles to the Internet of Things are enabled by integrated circuits (ICs) and their associated packages. The ICs have evolved from the early small-scale integration (SSI) to the later more complex very-large-scale integration (VLSI) and the subsequent ultra-large-scale integration (ULSI), in a continuous quest for improved functionality, higher performance, smaller form factors, and lower cost. The rate at which metal–oxide–semiconductor field-effect transistors (MOSFETs) counts on a chip have increased has generally followed Moore’s law, which states that the transistor count per chip doubles approximately every two years.

Synergy between dodecylbenzenesulfonic acid and isomeric alcohol polyoxyethylene ether for nano-scale scratch reduction in copper chemical mechanical polishing

In this paper, dodecylbenzenesulfonic acid (DBSA) and isomeric alcohol polyoxyethylene ether (iAEO) are tested as additives to basic silica-based slurries with the goal of reducing scratching during copper chemical mechanical polishing (CMP) in 14 nm ultra large scale integration. DBSA and iAEO can reduce scratch defects by more than 86% and exhibit stable scratch densities over 14 h of pad lifetime. Various analytical results including particle size distributions, large particle counts, dynamic mechanical analyses, and scanning electron microscope data reveal that the synergistic effects of DBSA and iAEO may improve particle dispersibility, enhance tribological behavior, increase pad water uptake, and effectively remove polishing byproducts from the pad.

Chromatic and Panchromatic Nonlinear Optoelectronic CMOSFETs for CMOS Image Sensors, Laser Multiplexing, Computing, and Communication

Traditionally, CMOS transistors are for low power, high speed, and high packing density applications. CMOS is also commonly used as power regulating devices, and light sensors (CCD or CMOS image sensors). In this paper, we would like to introduce Photonic CMOS as a light emitting device for optical computing, ASIC, power transistors, and ultra large scale integration (ULSI). A Photonic CMOS Field Effect Transistor is fabricated with a low-resistance laser or LED in the drain region, and multiple photon sensors in the channel / well regions. The MOSFET, laser, and photon sensors are fabricated as one integral transistor. With embedded nonlinear optical films, the Photonic CMOSFETs have the capability of detecting and generating focused laser beams of various frequencies to perform optical computing, signal modulation, polarization, and multiplexing for digital / analog processing and communication.

Damage to porous SiCOH low-k dielectrics by O, N and F atoms at lowered temperatures

Information on the degradation of porous organosilicate glasses (OSGs) by active radicals and atoms is of high importance for their integration as low-k dielectrics in the next generation of ultra large scale integration (ULSI) production. The films’ degradation is caused by depletion of coverage of the pore surface methyl. OSG samples with differing porosities and pore sizes were treated by O, N, and F atoms at lowered temperatures (down to −45 °С) downstream of O2, N2, and SF6 inductively coupled plasma discharges, respectively. It has been shown that lowering the temperature reduces film degradation. In the case of O atoms, this reduction is insignificant, while the effect is much more noticeable for F atoms. In addition, an accumulation of F atoms forms a fluorocarbon layer during F atom treatment. The accumulated fluorine can interact with surface Si atoms, giving rise to film etching. The film degradation under O and F atoms increases with pore size and porosity, due to deeper atom penetration. In the case of N atoms, even a small temperature reduction essentially decreases OSG degradation, while –CH3 modification is less clear in the cases of O and F atoms. Density functional theory and ab initio molecular dynamics simulations of reaction mechanisms show that atom reactions with surface Si–CH3 groups are the initial stages of OSG degradation. Subsequent mechanisms include branched reaction pathways with the formation, modification, and destruction of different surface groups. In the cases of O and F atoms, these reactions lead to the formation of HxCО and CFx bonds. For the direct reaction of N(4S) atoms with –СН3 groups, significant activation energy is required. Under downstream plasma conditions, –СН3 groups are destroyed in reactions with metastable particles, and first of all, with metastable atoms N(2D), N(2P) and molecules , which are also produced inside the pores in the surface recombination of nitrogen atoms.

Low-pressure chemical vapor deposition of Cu on Ru substrate using CuI: [formula omitted] calculations

We elucidate the molecular mechanism of Cu deposition using copper(I) iodide (CuI) on Ru substrate by low-pressure chemical vapor deposition through abinitio electronic structure calculations. Using density functional theory calculations, we show that CuI molecules adsorb and decompose exothermically due to a strong adsorption of iodine atoms onto the Ru(001) surface. The rate-limiting step of the Cu deposition is found to be the desorption of iodine molecules from the Cu(111) surface, suggesting that the removal of iodine species is necessary to achieve the high-rate deposition of highly-conductive copper films for ultra large scale integration metallization.

Key Technologies for Ultra Large-scale Integration

Key Technologies for Ultra Large-scale Integration