Ultra-thin Gate Oxide Layers Research Articles

A Modified 1/ Noise Model for MOSFETs With Ultra-Thin Gate Oxide

A modified 1/ $f$ noise model has been proposed for MOSFETs with an ultra-thin gate oxide layer. It is revealed that as the gate length $L$ deceases, the normalized drain current noise spectra density also decreases, which does not coincide with the regular 1/ $f$ noise theory. It is found that the trap-assisted gate leakage affects the drain current 1/ $f$ noise, and for the first time, it is demonstrated that the equivalent oxide trap density, the free carrier density, as well as $L$ determine the 1/ $f$ noise. A modified quantitative model is then proposed, which can well predict the 1/ $f$ noise.

Width Effect on Hot-Carrier-Induced Degradation for 90 nm Partially Depleted SOI CMOSFETs

The hot-carrier-induced degradation of partially depleted silicon-on-insulator complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) at various applied voltages was investigated using 90 nm body-contact silicon-on-insulator (BC-SOI) devices with 1.6 nm gate oxides and various gate widths. In this work, a small gate-width device with a large drain current density was observed to suffer from serious hot-carrier-induced degradation. By inspecting the gate current (IG) degradation, the quality of gate oxide was observed to decay apparently after hot-carrier stressing. For a 90 nm BC-SOI nMOSFET of 1.2 µm narrow gate width, the tolerance of 1.6 nm ultra thin gate oxide layer was very low particularly around the channel edge region; thus, device reliability is very critical and easily degraded because of device gate oxide breakdown after hot-carrier stressing.

Modeling negative bias temperature instabilities in hole channel metal–oxide–semiconductor field effect transistors with ultrathin gate oxide layers

The decrease of the threshold voltage Vth of hole channel metal–oxide–semiconductor field effect transistors with ultrathin gate dielectric layers under negative bias temperature stress is studied. A degradation model is developed that accounts for the generation of Si3≡Si• (Pb0) centers and bulk oxide defects, induced by the tunneling of electrons or holes through the gate dielectric layer during electrical stress. The model predicts that Vth shifts are mainly due to the tunneling of holes at low gate bias |VG|, typically below 1.5 V, while electrons are mainly responsible for these shifts at higher |VG|. Consequently, device lifetime at operating voltage, based on Vth shifts, should not be extrapolated from measurements performed at high gate bias. The impact of nitrogen incorporated at the Si/dielectric interface on Vth shifts is investigated next. The acceleration of device degradation when the amount of nitrogen increases is attributed to the increase in local interfacial strain, induced by the increase in bonding constraints, as well as to the increase in the density of Si–N–Si strained bonds that act as trapping centers of hydrogen species released during the electrical stress.

Effect of gate impurity concentration on inversion-layer mobility in MOSFETs with ultrathin gate oxide layer

In this paper, the influence of poly-Si-gate impurity concentration, N/sub poly/, on inversion-layer electron mobility is experimentally investigated in MOSFETs with ultrathin gate oxide layer. The split capacitance-voltage C-V method is modified to directly measure an effective mobility, paying attention to both 1) accurate current-voltage I-V and capacitance-voltage (C-V) measurements with high gate leakage current and 2) correct surface carrier density, N/sub s/, estimation at a finite drain bias. It is demonstrated that the mobility in ultrathin gate oxides becomes low significantly for highly doped gate, strongly suggesting the contribution of remote Coulomb scattering due to the gate impurities, which is quantitatively discriminated from that of Coulomb scattering due to substrate impurities and interface states. It is also found that the mobility lowering becomes significant rapidly at T/sub ox/ of 1.5 nm or less. The mobility-lowering component is weakly dependent on N/sub s/, irrespective of N/sub poly/, which cannot be fully explained by the existing theoretical models of remote impurity scattering.

Breakdown Modes and Their Evolution in Ultrathin Gate Oxide

Post-breakdown current–voltage characteristics of metal-oxide-semiconductor (MOS) devices with an ultrathin gate oxide layer have been carefully studied. Several breakdown modes were identified. Specifically, it was found that the typical soft-breakdown mode induced in an oxide layer thinner than 3 nm is actually quite different from that in an oxide layer thicker than 3 nm. Based on these findings, we have also proposed a model to explain the evolution of different breakdown modes. The model takes into consideration the thermal runaway process at the breakdown moment, and is substantiated by a number of experimental findings. Impacts of each breakdown mode on device switching behavior are also discussed.

Defect generation in ultrathin silicon dioxide films produced by anode hole injection

A direct demonstration of defect generation in ultrathin silicon dioxide films due to the transport of holes through this layer is reported. These defects are observed only when the hole current to the cathode of the device exceeds the electron current to the anode. This condition is produced on p-channel field-effect transistors under negative gate-voltage-bias conditions with ultrathin gate oxide layers. These results are related to current reliability models which use anode hole injection and the defects produced to explain destructive breakdown of the oxide layer.

Comparative physical and electrical metrology of ultrathin oxides in the 6 to 1.5 nm regime

In this work, five methods for measuring the thickness of ultra-thin gate oxide layers in MOS structures were compared experimentally on n/sup +/ poly-SiO/sub 2/-p-Si structures. Three methods are based on electrical capacitance-voltage (C-V) and current-voltage (I-V) data and the other two methods are HRTEM and optical measurement. MOS capacitors with oxide thickness in the range 17-55 /spl Aring/ have been used in this study. We found that thickness extracted using QM C-V and HRTEM agree within 1.0 /spl Aring/ over the whole thickness range when a dielectric constant of 3.9 was used. Comparison between thickness extracted using quantum interference (QI) I-V technique and optical measurement were also within 1.0 /spl Aring/ for thickness 31-47 /spl Aring/. However, optical oxide thickness was consistently lower than the TEM thickness by about 2 /spl Aring/ over the thickness range under consideration. Both optical measurement and QM C-V modeling yield the same thickness as the nominal oxide thickness increases (>50 /spl Aring/).

Relation between stress-induced leakage current and time-dependent dielectric breakdown in ultra-thin gate oxides

The stress-induced leakage current (SILC) of a 4.2 nm SiO2 layer is investigated during constant gate voltage stress of metal-oxide-semiconductor capacitors. The density of bulk electron traps generated during the electrical stress is extracted from the SILC contribution, assuming a trap-assisted tunnelling mechanism. It is shown that a fixed critical value for the density of traps is reached at breakdown or soft breakdown of the SiO2 layer, independent of the gate voltage stress. A physical model based on the formation of a percolation path between the bulk electron traps randomly generated during the stress is proposed to link SILC to time-dependent dielectric breakdown in ultra-thin gate oxides. The validity of this model with respect to positive and negative stress polarities is discussed. It is also shown that this model allows us to predict the reliability of ultra-thin gate oxide layers at low applied gate voltage stress.

Modeling Soft Breakdown of Ultra-Thin Gate Oxide Layers

ABSTRACTThe time-dependent dielectric breakdown of MOS capacitors with ultra-thin gate oxide layers is investigated. After the occurrence of soft breakdown, the gate current increases by 3 to 4 orders of magnitudes and behaves like a power law of the applied gate voltage. It is shown that this behavior can be explained by assuming that a percolation path is formed between the electron traps generated in the gate oxide layer during electrical stress of the capacitors. The time dependence of the gate voltage signal after soft breakdown is next analysed. It is shown that the fluctuations in the gate voltage are non-gaussian as well as that long-range correlations exist in the system after soft breakdown. These results can be explained by a dynamic percolation model, taking into account the trapping-detrapping of charges within the percolation cluster formed at soft breakdown.

Triggering and Suppression of Soft Breakdown During Mercury-Probe Assessment of Thin Gate Oxide Quality

ABSTRACTThe breakdown of ultra-thin gate oxide layers is investigated using fast-feedback Hg-probe measurements to perform Exponentially Ramped Current Stress (ERCS) tests. Several parameters have been varied in the ERCS test: oxide thickness (4nm, 5nm, 6nm and 7nm), capacitor area (0.12cm2 and 0.023cm2) and initial injected current (5×10−5 A and 5×10−4 A). Soft breakdown is detected only in case of oxides thinner than 5 nm. It is found that the fraction of points on the wafer on which soft breakdown occurs reduces by increasing the value of the injected current at the beginning of the ERCS test or completely disappears by decreasing the capacitor area. Consequences of current results for correct routine assessment of gate oxide integrity in microelectronic manufacturing are discussed.

Soft breakdown of ultra-thin gate oxide layers

The dielectric breakdown of ultra-thin 3 nm and 4 nm SiO/sub 2/ layers used as a gate dielectric in poly-Si gate capacitors is investigated. The ultra-thin gate oxide reliability was determined using tunnel current injection stressing measurements. A soft breakdown mechanism is demonstrated for these ultra-thin gate oxide layers. The soft breakdown phenomenon corresponds with an anomalous increase of the stress induced leakage current and the occurrence of fluctuations in the current. The soft breakdown phenomenon is explained by the decrease of the applied power during the stressing for thinner oxides so that thermal effects are avoided during the breakdown of the ultra-thin oxide capacitor. It is proposed that multiple tunnelling via generated electron traps in the ultra-thin gate oxide layer is the physical mechanism of the electron transport after soft breakdown. The statistical distributions of the charge to dielectric breakdown and to soft breakdown for a constant current stress of the ultra-thin oxides are compared. It is shown that for accurate ultra-thin gate oxide reliability measurements it is necessary to take the soft breakdown phenomenon into account.