Ultra-shallow Junctions Research Articles

The effect of silicon films impurity compensation on the performance of silicon drift detector

Silicon drift detector (SDD) fabricated using in-situ doping technology has been developed in recent years since its advantages of low process temperature and ultra-shallow junction. However, the N+ and P+ regions on the same substrate surface cannot be formed simultaneously during the process of fabricating SDD by using in-situ doping. To overcome these challenges, we proposed a simple method to form stacked silicon films with phosphorus doped layer and boron doped layer on the same surface of SDD by impurity compensation effect in this work. The stacked silicon films with thicker boron doped layer (stack-1, partially compensated) and thinner boron doped layer (stack-2, totally compensated) were prepared by impurity compensation. Then we further investigated the films properties and electrical properties of stack-1 and stack-2. The experimental results showed that the leakage current of stack-1 was larger than that of stack-2 in PN junction devices. The simulation results indicated that a tunnel junction was formed in the stack-1 which would cause a very large leakage current when a reverse bias was applied to the PN junction. Finally, stack-2 with completely compensated boron doped layer was used to fabricated SDD and the best energy resolution achieved at the temperature of 213 K was 180 eV @ the Mn-Kα line (5.9 keV). The good energy resolution of this SDD indicated that the stacked silicon films with fully compensated boron doped layer are suitable applied to fabricating the silicon drift detectors and can also obtain excellent device performance.

A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs.

This study proposed a novel source/drain (S/D) extension scheme to increase the stress in nanosheet (NS) field-effect transistors (NSFETs) and investigated the scheme by using technology-computer-aided-design simulations. In three-dimensional integrated circuits, transistors in the bottom tier were exposed to subsequent processes; therefore, selective annealing, such as laser-spike annealing (LSA), should be applied. However, the application of the LSA process to NSFETs significantly decreased the on-state current (Ion) owing to diffusionless S/D dopants. Furthermore, the barrier height below the inner spacer was not lowered even under on-state bias conditions because ultra-shallow junctions between the NS and S/D were formed far from the gate metal. However, the proposed S/D extension scheme overcame these Ion reduction issues by adding an NS-channel-etching process before S/D formation. A larger S/D volume induced a larger stress in the NS channels; thus, the stress was boosted by over 25%. Additionally, an increase in carrier concentrations in the NS channels improved Ion. Therefore, Ion increased by approximately 21.7% (37.4%) in NFETs (PFETs) compared with NSFETs without the proposed scheme. Additionally, the RC delay was improved by 2.03% (9.27%) in NFETs (PFETs) compared with NSFETs using rapid thermal annealing. Therefore, the S/D extension scheme overcame the Ion reduction issues encountered in LSA and significantly enhanced the AC/DC performance.

Study of Dopant Activation in Silicon Employing Differential Hall Effect Metrology (DHEM)

Differential Hall Effect Metrology (DHEM) technique was used to characterize highly n-type doped Si epi layers deposited on p-type Si wafers. Total dopant concentration, doping depth profile and post deposition annealing condition were changed for various sample sets and influence of such changes on the resistivity, mobility and carrier concentration depth profiles were studied. It was determined that samples annealed at 900 ∘C had higher activation compared to those annealed at 700 ∘C. Gradation in doping depth profiles did not result in similar gradation in resistivity values. Carrier concentration at the near-surface region was found to be lower in all samples. It is shown that electrical properties of films forming ultra-shallow junctions can be studied in detail and correlated with process parameters using DHEM data obtained at sub-nm depth resolution.

Fabrication of ultra-shallow junction by in situ doped amorphous silicon films and its application in silicon drift detectors

In situ doped amorphous silicon film, deposited by plasma enhanced chemical vapor deposition, is employed as a diffusion source to form an ultra-shallow junction and as voltage dividers in silicon drift detectors. By controlling annealing temperature and time, the junction depth can be adjusted precisely, and the shallowest junction depth of 15 nm is achieved. The I–V characteristics of the ultra-shallow junction, fabricated with different annealing temperature, annealing time and doping concentration, are then analyzed, and the reverse leakage current can be reduced to as low as 2 nA cm−2 under a reverse bias of 200 V at room temperature. The doped silicon film is also used to fabricate voltage dividers in silicon drift detectors. The sheet resistance of the silicon film is adjusted by controlling the thickness and annealing conditions, and a high resistance value and small temperature coefficient of the voltage dividers are achieved. Finally, the in situ doped amorphous silicon film is used to fabricate silicon drift detectors and the final energy resolution of 180 eV at 5.9 keV is achieved.

Differential nonlinear photocarrier radiometry for characterizing ultra-low energy boron implantation in silicon

The measuring of the depth profile and electrical activity of implantation impurity in the top nanometer range of silicon encounters various difficulties and limitations, though it is known to be critical in fabrication of silicon complementary metal–oxide–semiconductor (CMOS) devices. In the present work, SRIM program and photocarrier radiometry (PCR) are employed to monitor the boron implantation in industrial-grade silicon in an ultra-low implantation energy range from 0.5 keV to 5 keV. The differential PCR technique, which is improved by greatly shortening the measurement time through the simplification of reference sample, is used to investigate the effects of implantation energy on the frequency behavior of the PCR signal for ultra-shallow junction. The transport parameters and thickness of shallow junction, extracted via multi-parameter fitting the dependence of differential PCR signal on modulation frequency to the corresponding theoretical model, well explain the energy dependence of PCR signal and further quantitatively characterize the recovery degree of structure damage induced by ion implantation and the electrical activation degree of impurities. The monitoring of nm-level thickness and electronic properties exhibits high sensitivity and apparent monotonicity over the industrially relevant implantation energy range. The depth profiles of implantation boron in silicon with the typical electrical damage threshold (Y ED) of 5.3 × 1015 cm−3 are evaluated by the SRIM program, and the determined thickness values are consistent well with those extracted by the differential PCR. It is demonstrated that the SRIM and the PCR are both effective tools to characterize ultra-low energy ion implantation in silicon.

Nano-Scale Depth Profiles of Electrical Properties of Phosphorus Doped Silicon for Ultra-Shallow Junction Evaluation

Electrical properties and microstructure of phosphorus (P) implanted p-type Si substrates were evaluated by four-point probe (4PP), Differential Hall Effect Metrology (DHEM), secondary ion mass spectrometry (SIMS) and transmission electron microscopy (TEM) techniques, after RTA 750-950°C and CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> laser 120-140W annealing. When RTA temperature was increased, defect concentration at a-Si/c-Si interface gradually disappeared. For CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> laser annealing, defects were found to aggregate at the end of range (EOR) region. Sheet resistance (Rs) values decreased significantly with increasing RTA temperature due to defects disappearing at EOR. Rs did not change appreciably for the CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> laser annealing case. The dopant activation ratio was less than 50% below RTA temperature of 850 °C, and it increased to 70% at 950 °C. For CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> laser annealing, the activation ratio could reach to over 80% regardless of the laser power. The highest active concentration and the lowest resistivity or mobility were found to be within the top 20 nm region of the surface. Although RTA annealing conditions influenced dopant diffusion and the resulting electrical property depth profiles significantly, depth profiles did not change much with changes in CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> laser power level. It was demonstrated that DHEM data in conjunction with SIMS and TEM data can be successfully employed to evaluate, in detail, the electrical properties of ultra-shallow junctions for metal oxide semiconductor field effect transistor (MOSFET) applications.

Ultrashallow Junction Electrodes in Low-Loss Silicon Microring Resonators

Electrodes in close proximity to an active area of a device are required for sufficient electrical control. The integration of such electrodes into optical devices can be challenging since low optical losses must be retained to realise high quality operation. Here, we demonstrate that it is possible to place a metallic shallow phosphorus doped layer in a silicon micro-ring cavity that can function at cryogenic temperatures. We verify that the shallow doping layer affects the local refractive index while inducing minimal losses with quality factors up to 10$^5$. This demonstration opens up a pathway to the integration of an electronic device, such as a single-electron transistor, into an optical circuit on the same material platform.

Ultrashallow Junction (USJ) Fabrication by Advanced Ion Implantation Processes

For advanced CMOS device process, a preamorphization implant (PAI) procedure had been carried on source and drain (SD) lightly doped source and drain (LDD), heavily doped source and drain (HDD), and contact implants before an ultralow energy (ULE) beamline (BL)-based implant to depress the channeling effect for lower OFF-current and short channel effect (SCE). One-step plasma doping (PLAD) was utilized to replace this two-step BL implant process for the pMOS device because PLAD has an in situ real-time controllability for less channeling effect. The PLAD using B <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> gas with ULE high dose regime was utilized for this application. It significantly reduces cost and increases throughput because this one low-cost PLAD module eliminates PAI BL implant. The pMOS devices also exhibit significant performance improvements, including ~30% lower contact resistances ( <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CS</sub> ), similar threshold voltage ( <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and subthreshold voltage (SV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) characteristics, and ~8% higher drive currents (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>DS</b></sub> ) without degrading OFF-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ).

High-resolution Rutherford backscattering spectrometry with an optimised solid-state detector

Rutherford Backscattering Spectrometry (RBS) is a powerful ion beam analysis technique in frequent use within materials science. The recent emergence of targets incorporating complex features such as ultra-scaled diffusion barriers and isotopically-enriched films has started to push the limits of the technique, necessitating the expanded use of systems with a higher energy resolution. The increased cost and complexity of these systems based on already well-established schemes may present a barrier to their more widespread adoption. Here, we present an RBS detection system specifically designed for simple integration into existing nuclear probe infrastructure, but with a considerably higher energy resolution than a standard passivated planar detector. We employ a modified silicon p–i–n photodiode integrated within an optimised in-vacuum preamplifier to achieve a relative energy resolution of 3 × 10−3 with 2.2 MeV He+ ions. In a glancing angle geometry, this corresponds to a depth resolution of ∼1.5nm and a mass resolution of <1u from light elements up to Cu. We demonstrate the use of this detector to measure the thermal diffusion of near-surface As implants in a Si substrate, important for the formation of ultra-shallow junctions; and the residual 29Si concentration in an isotopically enriched 28Si specimen, a promising platform for quantum computation.

Camphor-Based CVD Bilayer Graphene/Si Heterostructures for Self-Powered and Broadband Photodetection.

This work demonstrates a self-powered and broadband photodetector using a heterojunction formed by camphor-based chemical vaper deposition (CVD) bilayer graphene on p-Si substrates. Here, graphene/p-Si heterostructures and graphene layers serve as ultra-shallow junctions for UV absorption and zero bandgap junction materials (<Si bandgap (1.1 eV)) for long-wave near-infrared (LWNIR) absorption, respectively. According to the Raman spectra and large-area (16 × 16 μm2) Raman mapping, a low-defect, >95% coverage bilayer and high-uniformity graphene were successfully obtained by camphor-based CVD processes. Furthermore, the carrier mobility of the camphor-based CVD bilayer graphene at room temperature is 1.8 × 103 cm2/V·s. Due to the incorporation of camphor-based CVD graphene, the graphene/p-Si Schottky junctions show a good rectification property (rectification ratio of ~110 at ± 2 V) and good performance as a self-powered (under zero bias) photodetector from UV to LWNIR. The photocurrent to dark current ratio (PDCR) value is up to 230 at 0 V under white light illumination, and the detectivity (D*) is 8 × 1012 cmHz1/2/W at 560 nm. Furthermore, the photodetector (PD) response/decay time (i.e., rise/fall time) is ~118/120 μs. These results support the camphor-based CVD bilayer graphene/Si Schottky PDs for use in self-powered and ultra-broadband light detection in the future.

Well-behaved Ge n+/p shallow junction achieved by plasma immersion ion implantation

Ge n+/p junctions fabricated by conventional ion implantation (CII) and plasma immersion ion implantation (PIII) are compared in this work. To achieve low junction leakage current, PIII-implanted Ge n+/p junctions require higher annealing temperature to eliminate the Shockley-Read-Hall generation current, which may be contributed to the residual hydrogen and hydrogen-related defects. It is demonstrated that with 500 °C annealing, well-behaved Ge n+/p junction with ultra-shallow junction depth (<50 nm) can be achieved by PIII. With 600 °C annealing, best Ge n+/p junction performance with current on/off ratio ~9 × 105 and ideality factor ~1.07 is achieved by PIII.

Total ionization dose effects of N-type tunnel field effect transistor (TFET) with ultra-shallow pocket junction

N-type tunnel field effect transistors (TFETs) with Si1−xGex/Si hetero-junction in the ultra-shallow N+ pocket region have been fabricated. This paper investigates the total ionization dose (TID) effects on the electrical characteristics of these N-type TFET devices, including transfer and output characteristics, via a 60Co γ-ray irradiation source. TID has little impact on the on-state current for TFETs with and without P well. With the increase in total dose, however, a shift in the transfer characteristics, such as the off-state current and subthreshold slope is observed. Under the same TID condition, TFETs with P well exhibit more robustness as compared to TFETs without P well. The characteristics under room temperature and high temperature annealing conditions after irradiation are also investigated. The underlying mechanisms, such as the interplay among bulk trapped charge in gate oxide-induced inversion and interface trap-induced trap-assisted-tunneling, are identified by TCAD simulation and are discussed in detail.

Conformal and Ultra Shallow Junction Formation Achieved Using a Pulsed-Laser Annealing Process Integrated With a Modified Plasma Assisted Doping Method

Recently, a shallow and conformal doping profile is required for promising 3D structured devices. In this study, we deposited the dopant phosphorus (P) using modified plasma assisted doping (PaD) followed by an annealing process to electrically activate the dopants. A rapid thermal annealing process (RTP) was the first approach tested for activation but it resulted in a deep junction (>35 nm). To reduce the junction depth, we tried the flash lamp annealing process (FLP) to shorten the annealing time. We also predicted the annealing temperature by numerical thermal analysis, which reached 1,020 °C. However, the FLP resulted in a deep junction (~ 30 nm), which was not shallow enough to suppress short channel effects. Since an even shorter annealing process was required to form a ultra-shallow junction, we tried the laser annealing process (LAP) as a promising alternative. The LAP, which had a power density of 0.3 J/cm2, increased the surface temperature up to 1,100 °C with a shallow isothermal layer. Using the LAP, we achieved a USJ with an activated surface dopant concentration of $3.86\times 10 ^{19}$ cm−3 and a junction depth of 10 nm, which will allow further scaling-down of devices.

Epitaxial n++-InGaAs ultra-shallow junctions for highly scaled n-MOS devices

High electron mobility III-V semiconductors like InGaAs are excellent candidates for sub-10 nm n-metal-oxide-semiconductor (nMOS) devices. One of the critical challenges in downscaling III-V devices is achieving low-resistance contacts by forming low-defect, ultra-shallow junctions <9 nm in depth, with n-type dopant concentrations above 1019 cm−3. In the current study, we combine time-of-flight secondary ion mass spectrometry (ToF-SIMS) depth profile analysis, atomic force microscopy (AFM) imaging, and high-resolution transmission electron microscopy (HR-TEM) to determine the optimal doping strategy for growing Si-doped n++-In0.25Ga0.75As ultra-shallow junctions by molecular beam epitaxy. We test three different approaches to doping: homogeneous co-deposition, single δ-layer (continuous) doping, and triple δ-layer (pulsed) doping. We demonstrate the formation of technologically suitable n++-In0.25Ga0.75As junctions 5–7 nm deep, grown under As-rich conditions with a single δ-layer at temperatures as low as 400 °C. These junctions have peak Si concentrations between 6 × 1019 and 1 × 1020 cm−3 and high crystal quality. The surface self-organizes into smooth ripples or mounds, up to a peak dopant concentration of ~2 × 1020 cm-3. Above this value, enhanced diffusion of Si and In due to a large population of Ga vacancies increases lattice strain in the semiconductor epilayer, triggering a transition from 2D growth to 3D growth and the formation of In0.85Ga0.15As clusters on the surface.

Low-Temperature Hybrid Dopant Activation Technique Using Pulsed Green Laser for Heavily-Doped n-Type SiGe Source/Drain

We present a novel hybrid dopant activation technique for n-type silicon–germanium (SiGe) to achieve high doping concentration and ultra-shallow junction at low temperature (≤500 °C) using rapid thermal annealing and pulsed green laser post-annealing (hybrid RTA-GLA). The hybrid RTA-GLA process achieved one of the highest surface and peak doping concentrations of $1.82\times 10^{\textsf {20}}$ cm−3 and $9.27\times 10^{\textsf {20}}$ cm−3, respectively, compared with low-temperature doping techniques for n-type SiGe. In addition, the n-type SiGe films doped by the hybrid RTA-GLA process provide ultra-shallow (<60 nm) and abrupt (5 nm/decade) junctions. This advanced low-temperature hybrid dopant activation technique is a promising method for developing SiGe-based electronics.

Low-temperature activation of boron ion in silicon substrate using B10H14+ cluster and by soft X-ray irradiation

To achieve an ultrashallow junction, a novel activation method for a B dopant in a Si wafer using a soft X-ray undulator in a synchrotron radiation facility was proposed. In addition, B10H14+ clusters were used to obtain high activation ratios and small junction depths. A low-sheet resistance of 245 Ω/sq was obtained using B10H14+ clusters and by soft X-ray irradiation at 490 °C. A p–n junction was fabricated at a treatment temperature of 440 °C without excessive dopant diffusion. The mechanism of low-temperature activation by soft X-ray irradiation is discussed in comparison with that of conventional furnace annealing and on the basis of the difference between B+ and B10H14+ clusters.

A variable probe pitch micro-Hall effect method.

Hall effect metrology is important for a detailed characterization of the electronic properties of new materials for nanoscale electronics. The micro-Hall effect (MHE) method, based on micro four-point probes, enables a fast characterization of ultrathin films with minimal sample preparation. Here, we study in detail how the analysis of raw measurement data affects the accuracy of extracted key sample parameters, i.e., how the standard deviation on sheet resistance, carrier mobility and Hall sheet carrier density is affected by the data analysis used. We compare two methods, based primarily on either the sheet resistance signals or the Hall resistance signals, by theoretically analysing the effects of electrode position errors and electrical noise on the standard deviations. We verify the findings with a set of experimental data measured on an ultrashallow junction silicon sample. We find that in presence of significant electrical noise, lower standard deviation is always obtained when the geometrical analysis is based on the sheet resistance signals. The situation is more complicated when electrode position errors are dominant; in that case, the better method depends on the experimental conditions, i.e., the distance between the insulating boundary and the electrodes. Improvement to the accuracy of Hall Effect measurement results is crucial for nanoscale metrology, since surface scattering often leads to low carrier mobility.

Effects of oxygen-inserted layers on diffusion of boron, phosphorus, and arsenic in silicon for ultra-shallow junction formation

The effects of oxygen-inserted (OI) layers on the diffusion of boron (B), phosphorus (P), and arsenic (As) in silicon (Si) are investigated, for ultra-shallow junction formation by high-dose ion implantation followed by rapid thermal annealing. The projected range (Rp) of the implanted dopants is shallower than the depth of the OI layers. Secondary ion mass spectrometry is used to compare the dopant profiles in silicon samples that have OI layers against the dopant profiles in control samples that do not have OI layers. Diffusion is found to be substantially retarded by the OI layers for B and P, and less for As, providing shallower junction depth. The experimental results suggest that the OI layers serve to block the diffusion of Si self-interstitials and thereby effectively reduce interstitial-aided diffusion beyond the depth of the OI layers. The OI layers also help to retain more dopants within the Si, which technology computer-aided design simulations indicate to be beneficial for achieving shallower junctions with lower sheet resistance to enable further miniaturization of planar metal-oxide-semiconductor field-effect transistors for improved integrated-circuit performance and cost per function.

Shallow Si N + P junction diodes realized via molecular monolayer doping

A conformal and controlled semiconductor doping is needed for applications in next generation nanoscale devices, low contact resistivity metal semiconductor junctions such as selective emitters in solar cells. Molecular monolayer doping (MLD) in silicon is a novel technique based on the formation of self-assembled monolayer of dopant – containing molecules on surface of crystalline silicon, followed by rapid thermal anneal. The technique is capable of forming ultra-shallow junctions with high atomic accuracy and minimum defects in silicon. A container and process was developed which successfully doped 6in. diameter silicon wafers using MLD for the in-house CMOS fabrication facility. The phosphorus monolayer is grafted on hydrogen terminated p-type silicon followed by rapid thermal anneal. Average sheet resistance ~670Ω/sq. and junction depth ~25nm are achieved. N+P junctions are fabricated using MLD and current-voltage characteristics are measured and analyzed using unified diode model.

Deep level transient spectroscopic investigation of phosphorus-doped silicon by self-assembled molecular monolayers

It is known that self-assembled molecular monolayer doping technique has the advantages of forming ultra-shallow junctions and introducing minimal defects in semiconductors. In this paper, we report however the formation of carbon-related defects in the molecular monolayer-doped silicon as detected by deep-level transient spectroscopy and low-temperature Hall measurements. The molecular monolayer doping process is performed by modifying silicon substrate with phosphorus-containing molecules and annealing at high temperature. The subsequent rapid thermal annealing drives phosphorus dopants along with carbon contaminants into the silicon substrate, resulting in a dramatic decrease of sheet resistance for the intrinsic silicon substrate. Low-temperature Hall measurements and secondary ion mass spectrometry indicate that phosphorus is the only electrically active dopant after the molecular monolayer doping. However, during this process, at least 20% of the phosphorus dopants are electrically deactivated. The deep-level transient spectroscopy shows that carbon-related defects are responsible for such deactivation.