Ultra-low Power Low Noise Amplifier Research Articles

A 30–50-GHz Ultralow-Power Low-Noise Amplifier With Second-Stage Current-Reuse for Radio Astronomical Receivers in 90-nm CMOS Process

A Q-band (30–50 GHz) ultralow-power low-noise amplifier (LNA) for radio astronomical receivers in 90-nm CMOS technology is presented in this letter. A common source stage with source degeneration is utilized for simultaneous noise and impedance matching. To achieve high gain and low power consumption, the current-reused technique is adopted in this work. According to measurement, the proposed Q-band LNA achieves a 20.5-dB small signal gain with 26-GHz 3-dB bandwidth (25.5–51.5 GHz) and the lowest in-band noise figure (NF) of 4.2-dB noise. The LNA consumes only 10.1 mW with a compact chip area of 0.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . Although this LNA is fabricated in 90-nm CMOS process, it achieves the state-of-the-art figure of merit (FOM) compared to other advanced CMOS processes.

A 219-\xb5W ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

Due to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain (S21) of 18.87 dB, minimum noise figure ({NF}_{min.}) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of 0.40{mathrm{ mm}}^{2} and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

Ultra-low power 0.45 mW 2.4 GHz CMOS low noise amplifier for wireless sensor networks using 0.13-m technology

This paper describes the design topology of a ultra-low power low noise amplifier (LNA) for wireless sensor network (WSN) application. The proposed design of ultra-low power 2.4 GHz CMOS LNA is implemented using 0.13-μm Silterra technology. The LNA benefits of low power from forward body bias technique for first and second stages. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The simulation results show that the total power consumed is only 0.45 mW at low supply voltage of 0.55 V. The power consumption is decreased about 36% as compared with the previous work. A gain of 15.1 dB, noise figure (NF) of 5.9 dB and input third order intercept point (IIP3) of -2 dBm are achieved. The input return loss (S11) and the output return loss (S22) is -17.6 dB and -12.3 dB, respectively. Meanwhile, the calculated figure of merit (FOM) is 7.19 mW-1.

Ultra-Low Power 0.55 mW 2.4 GHz CMOS Low-Noise Amplifier for Wireless Sensor Network

This paper describes the design topology of two-stage ultra-low power low noise amplifier (LNA) using the forward body bias technique for wireless sensor network (WSN) application. The proposed design employs CMOS 0.13-µm technology at 2.4 GHz frequency. The LNA consumes low power from the forward body bias technique at the first and the second stages. The threshold voltage of the transistor can be lowered using the forward body bias technique. Two stages are implemented in order to enhance the gain while obtaining low power consumption for overall circuit. The measurement results show that the LNA consumes a total power of 0.55 mW at supply voltage 0.55 V. The input return loss (S11) and the output return loss (S22) is 10 and 12 dB, respectively. A gain of 12 dB, noise figure (NF) of 5.9 dB and input third-order intercept point (IIP3) of −3 dBm are achieved.

Ultra-low power LNA design technique for UWB applications

In this paper, a design technique to improve low noise amplifier (LNA) performance is proposed. This technique is based on a new operating parameter (OP) of MOSFETs for radio frequency (RF) applications. This technique is used to optimize low noise amplifier (LNA) parameters for Ultra-Wideband (UWB) applications. The presented methodology predicts the optimum biasing point to maximize LNA performance. Simulation results show that the proposed methodology can increase the figure of merit (FoM) by 70% compared to traditional methodologies, without having a significant effect on either noise figure (NF) or linearity characteristics.

초 저전력 CMOS 2.4 GHz 저잡음 증폭기 설계

In this paper, we proposed an ultra-low power low noise amplifier(LNA) using a TSMC 0.18 RF CMOS process. To satisfy the low power consumption with high gain, a current-reused technique is utilized. In addition, a low bias voltage in the subthreshold region is utilized to achieve ultra low power characteristic. The designed LNA has the voltage gain of 13.8 dB and noise figure(NF) of 3.4 dB at 2.4 GHz. The total power consumption of the designed LNA is only 0.63 mW from 0.9 V supply voltage and chip occupies area.