Ultra Large Scale Integration Technology Research Articles

Advancement and Challenges of Biosensing Using Field Effect Transistors.

Field-effect transistors (FETs) have become eminent electronic devices for biosensing applications owing to their high sensitivity, faster response and availability of advanced fabrication techniques for their production. The device physics of this sensor is now well understood due to the emergence of several numerical modelling and simulation papers over the years. The pace of advancement along with the knowhow of theoretical concepts proved to be highly effective in detecting deadly pathogens, especially the SARS-CoV-2 spike protein of the coronavirus with the onset of the (coronavirus disease of 2019) COVID-19 pandemic. However, the advancement in the sensing system is also accompanied by various hurdles that degrade the performance. In this review, we have explored all these challenges and how these are tackled with innovative approaches, techniques and device modifications that have also raised the detection sensitivity and specificity. The functional materials of the device are also structurally modified towards improving the surface area and minimizing power dissipation for developing miniaturized microarrays applicable in ultra large scale integration (ULSI) technology. Several theoretical models and simulations have also been carried out in this domain which have given a deeper insight on the electron transport mechanism in these devices and provided the direction for optimizing performance.

Inhibition Effect of TT-LYK on Cu Corrosion and Galvanic Corrosion between Cu and Co during CMP in Alkaline Slurry

Cu corrosion and galvanic corrosion between Cu and Co are two challenging issues during the chemical mechanical polishing (CMP) process in the ultra large scale integration (ULSI) technology. The effect of novel inhibitor TT-LYK on Cu corrosion and galvanic corrosion between Cu and Co in alkaline slurry was investigated under both static and dynamic conditions. Various analytical techniques were used to elucidate the corrosion inhibition mechanism of TT-LYK on Cu. Results showed that both static etching rate (SER) and removal rate (RR) of Cu during CMP decreased with the increase of concentration of TT-LYK. From potentiodynamic polarization, electrochemical impedance spectroscopy (EIS), X-ray photoelectron spectroscopy (XPS) measurements, it was found that the corrosion inhibition effect on Cu may result from the adsorption of Cu(I)-TT-LYK passivating film on Cu surface. In order to characterize the effect of galvanic corrosion, the corrosion potential difference (△E) between Cu and Co was measured during both static and dynamic condition. It was apparently seen from the results that the galvanic corrosion under dynamic conditions was significantly suppressed compared with the static cases. It revealed that if the experiments had only been conducted under static conditions, the results would have been considerably misleading.

Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Vertically stacked dielectric separated independently controlled gates can be used to realize dual-threshold voltage on a single silicon channel MOS device. This approach significantly reduces the effective layout area and is similar to merging two transistors in series. This multiple independent gate device enables the design of new class of compact logic gates with low power and reduced area. In this paper, we present the junctionless concept based twin gate transistor for digital applications. To analyse the appropriate behaviour of device, this paper presents the modeling, simulation and digital overview of novel gate-all-around junctionless nanowire twin-gate transistor for advanced ultra large scale integration technology. This low power single MOS device gives the full functionality of "AND" gate and can be extended to full functionality of 2-input digital "NAND" gate. To predict accurate behaviour, a physics based analytical drain current model has been developed which also includes the impact of gate depleted source/drain regions. The developed model is verified using ATLAS 3D device simulator. This single channel device can function as "NAND" gate even at low operating voltage.

Removal of Interfacial Layer in HfO<sub>2</sub> Gate Stack by Post-Gate Cleaning Using NF<sub>3</sub>/NH<sub>3</sub> Dry Cleaning Technique

HfO2 gate stack has been one of the most popular subjects of research in recent years due to its outstanding material properties, such as high-k (20~25), wide band gap (~5.68eV), and the compatibility with Si-based semiconductor process technology. However, the interfacial layer (IL) with a reduced k-value between HfO2 dielectric and Si channel is still a critical issue for future ultra large scale integration (ULSI) technology application of the HfO2 gate stack. Various ways have been studied to improve the IL properties of HfO2 gate stack and to achieve ~1nm-thick equivalent oxide thickness (EOT) of the gate stack. Recently, fluorine incorporations into the HfO2 gate stack have been suggested for improvement of the electrical properties of the gate stack by defect passivation.1,2 However, it was reported that the SiOx IL grows during the fluorine treatment of HfO2 film, which finally led to degradation of electrical characteristics.2 In this paper, we present interesting findings on the IL removal effect of fluorine incorporation into the HfO2 gate stack where a post-gate dry cleaning technique is used with the NF3/NH3 plasma.

Biosensor integration on Si-based devices: Feasibility studies and examples

Feasibility studies and examples of integration of Si-based miniaturized biosensors are discussed. We investigated three main issues: (i) device surface functionalization, (ii) biological molecule functionality after immobilization and (iii) biosensor working principle using electrical transduction mechanism in order to fabricate electrolyte-insulator-semiconductor (EIS) and, in the near future, ion-sensitive field-effect transistor (ISFET) biosensors.We compared a well established method for the immobilization of bio-molecules on Si oxide with a new immobilization protocol, both providing a covalent bonding on SiO2 surfaces of proteins (metallothioneines) enzymes (glucose oxidase, horse radish peroxidase), or DNA strands. The process steps were characterized by means of contact angle, XPS and TEM measurements. The compatibility with Ultra Large Scale Integration (ULSI) technology of the two protocols was also studied. The results strongly encourage to use the new optimized protocol to accomplish both ULSI compatibility and biological molecules correct functionalization. The electrical characterization of MOS-like capacitors with ssDNA anchored on the SiO2 dielectric, allowed us to conclude that the structures tested are sensitive to DNA immobilization and hybridization, as demonstrated by a positive shift in the VFB of +0.47±0.04V after ssDNA immobilization and by a further +0.07±0.02V shift when hybridization occurs. Device working principle was proved in this way. However, our results seem to indicate that bare SiO2 surfaces cannot be used as anchoring sites for DNA in transistor applications. In fact, the immersion in solution causes the migration of H+ ions in the oxide and the formation of defects at the SiO2/Si interface.

Understanding stress gradients in microelectronic metallization

The manufacture of ultra-large scale integration technology can impose significant strain within the constituent metallization because of the mismatch in coefficients of thermal expansion between metallization and its surrounding environment. The resulting stress distributions can be large enough to induce voiding within Cu-based metallization, a key reliability issue that must be addressed. The interface between the Cu and overlying capping layers is a critical location associated with void formation. By combining conventional and glancing-incidence X-ray diffraction, depth-dependent stress distributions that develop in Cu films and patterned features are investigated. In situ annealing and as-deposited measurements reveal that strain gradients are created in capped Cu structures, where an increased in-plane tensile stress is generated near the Cu/cap interface. The interplay between plasticity in Cu and the constraint imposed by capping layers dictates the extent of the observed gradients. Cu films possessing caps deposited at temperatures where Cu experienced only elastic deformation did not exhibit depth-dependent stress distributions. However, all capped Cu samples exposed to temperatures that induce plastic behavior developed greater tensile stress at the Cu/cap interface than in the bulk Cu film after cooling, representing a clear concern for the mitigation of metallization voiding.

Co‐Implantation of Carbon and Protons: An Integrated Silicon Device Technology Compatible Method to Generate the Lasing G‐Center

AbstractThe optically active carbon related G‐center is attracting great interest because of evidence that it can provide lasing in silicon. Here a technique to form the G‐center in silicon is reported. The carbon G‐center is generated by implantation of carbon followed by proton irradiation. Photoluminescence measurements confirm the controlled formation of high levels of the G‐center that, importantly, completely dominates the emission spectrum. Unlike previous methods of introducing the G‐center the current approach significantly is truly fully compatible with standard silicon ULSI (ultralarge scale integration) technology.

Evolution of stress gradients in Cu films and features induced by capping layers

The presence of voids in Cu metallization represents a key reliability issue for ultra-large scale integration technology. In particular, the interface between the Cu and capping layers represents a critical location where the stress state of the Cu must be experimentally determined. Glancing-incidence X-ray diffraction (GIXRD) can be used to investigate depth-dependent stress distributions within electroplated Cu films induced by overlying capping layers. A combination of conventional X-ray diffraction measurements and GIXRD results revealed that strain gradients were created in Cu films and patterned features possessing a SiCxNyHz cap, where an increased in-plane tensile stress was generated near the film/cap interface due to the constraint imposed by the SiCxNyHz layer during cooling from the cap deposition temperature. Cu films possessing a CoWP cap, deposited at lower temperatures where the Cu experienced only elastic deformation, did not exhibit depth-dependent stress distributions. However, all Cu samples exposed to the SiCxNyHz deposition temperature developed stress gradients regardless of the capping material. Although in situ annealing of SiCxNyHz capped Cu films decreased the stress gradient as the sample temperature approached that of the cap deposition, the gradient reappeared upon cooling to room temperature.

Ge-Based Silicon–Oxide–Nitride–Oxide–Silicon-Type Nonvolatile Memory Formed on Si Substrate

With Si substrate, the silicon–oxide–nitride–oxide–silicon-type nonvolatile memory formed on a Ge layer with thermal as the tunnel dielectric is explored in this work. The promising performance of the Ge-based memory is evidenced by the large hysteresis memory window, the high operation speed of 4.2 V flatband voltage shift by erasing at −16 V for 1 ms, the negligible memory window degradation up to operation cycles, and a good retention characteristic with 15% charge loss after a 10 year operation. The asymmetry in programming and erasing speed is observed, and the mechanism, along with the approaches to alleviate this phenomenon, is also discussed. Most importantly, the Ge-based memory device can be implemented by the process fully compatible with existent ultralarge-scale integration technology, paving the way to enable high performance nonvolatile memory for the next-generation electronic system.

Deposition and characterization of electroless Ni–Co–P alloy for diffusion barrier applications

Electroless deposited NiP and NiCoP thin films were studied for their diffusion barrier properties for copper wiring in ultra-large scale integration (ULSI) technology. The thermal stability of the Si/NiP/Cu and Si/NiCoP/Cu structures was evaluated by X-ray diffractometer (XRD), four probe method and field emission-scanning electron microscope (FE-SEM). Results indicated that both structures, i.e. Si/NiP/Cu and Si/NiCoP/Cu are thermally stable up to 500 °C. Further annealing results in formation of various silicided phases.

Nonvolatile Memory With TiN Nanocrystals Three-Dimensionally Embedded in $\hbox{Si}_{3}\hbox{N}_{4}$ Formed by Spinodal Phase Segregation

In this letter, TiN nanocrystals three-dimensionally embedded in the Si3N4 formed by spinodal phase segregation was investigated as the discrete charge-trapping layer in a metal-oxide-nitride-oxide-silicon structure for nonvolatile-memory applications. TiN-nanocrystal formation was verified by X-ray diffraction analysis while the 3-D distribution of nanocrystals in the Si3N4 film was confirmed by transmission electron microscopy with the average size of 5.1 nm and a density of 9.8 t 1011cm-2. The promising memory performance was evidenced by the large memory window of 1.81 V with plusmn4-V program/erase voltage, the high operation speed of 1.52-V threshold-voltage shift by programming at +4 V for 10 ms, the negligible memory-window degradation up to 105 operation cycles, and 11% charge loss after ten-year operation. Most importantly, the charge-storage structure can be formed by a cosputtering approach which is simple and fully compatible with existent ultralarge scale integration technology.

Improvement of Silicon-Based Thin Film Transistor Performances by Modifying Technological Fabrication Process Steps: a Similar Approach with ULSI Technology

The silicon based thin film transistors technological process evolution is governed by electrical performance improvements that are needed for the numerous fields of large area electronic applications. In fact, the electrical properties of the TFTs are directly linked to many aspects combining efforts to improve the process steps by several ways. All these approaches are similar to the ultra large scale integration technology (ULSI) ones. The goal of this paper is to highlight these similarities. After the presentation of the evolution during the last twenty years of the TFT processes, we will discuss on the common approaches between nano- and giga- electronics in order to show that their basic scientific principles are roughly the same.

Deterministic plasma-aided synthesis of high-quality nanoislanded nc-SiC films

Despite major advances in the fabrication and characterization of SiC and related materials, there has been no convincing evidence of the synthesis of nanodevice-quality nanoislanded SiC films at low, ultralarge scale integration technology–compatible process temperatures. The authors report on a low-temperature (400°C) plasma-assisted rf magnetron sputtering deposition of high-quality nanocrystalline SiC films made of uniform-size nanoislands that almost completely cover the Si(100) surface. These nanoislands are chemically pure, highly stoichiometric, have a typical size of 20–35nm, and contain small (∼5nm) nanocrystalline inclusions. The properties of nanocrystalline SiC films can be effectively controlled by the plasma parameters.

Electroless Diffusion Barrier Process Using SAM on Low-k Dielectrics

A wet process based on electroless deposition is proposed for the formation of a diffusion barrier layer for Cu wiring in ultra-large scale integration (ULSI) technology. The diffusion barrier layer is formed on a low-dielectric constant (low-) inter level film. In this process, a Pd-activated self-assembled monolayer as a seed/adhesion layer was used as a key step to allow electroless deposition on a dielectric film. The effectiveness of this approach was demonstrated by depositing an electroless layer as the diffusion barrier layer. The electrolessly deposited layer showed a uniform surface, a small grain size, and a high adhesion when deposited on various common inter level dielectric materials with low dielectric constant. The electrolessly deposited layer formed on the low- dielectric film by this method showed a high thermal stability of the effectiveness as a barrier to Cu diffusion at temperatures up to for . The electroless process was found to be reproducible and did not affect dielectric properties of the underlying insulator.

Novel MIS Ge–Si Quantum-Dot Infrared Photodetectors

The metal-insulator-semiconductor (MIS) Ge-Si quantum-dot infrared photodetectors (QDIPs) are successfully demonstrated. Using oxynitride as gate dielectric instead of oxide, the operating temperature reaches 140 and 200 K for 3-10 and 2-3 /spl mu/m detection, respectively. From the photoluminescence spectrum, the quantum-dot structures are responsible for the 2-3 /spl mu/m response with high operation temperature, and the wetting layer structures may be responsible for the 3-10 /spl mu/m response. This novel MIS Ge-Si QDIP can increase the functionality of Si chip such as noncontact temperature sensing and is compatible with ultra-large scale integration technology.

Direct CoSi[sub 2] thin-film formation with homogeneous nanograin-size distribution by oxide-mediated silicidation

By annealing at 460°C for 120s followed by 600°C120s, nanocrystalline CoSi2 thin film with an average grain size of 5nm can be directly formed from a Co∕SiOx∕Si multilayer with the SiOx as a mediated layer. It is found that annealing at 460°C for enough time is crucial for generating enough diffusion channels within the SiOx layer. After these channels are created, subsequent annealing at 600°C keeps these channels open and is responsible for rapid grain growth. In other words, by using two-step annealing, nucleation and growth processes can be effectively controlled and, hence, the resulting microstructure. The homogeneous nanograin-size distribution is important for ultralarge-scale integration technology below 90nm to prevent resistance degradation induced by CoSi2 agglomeration.

Boron-Retarded Gate Dielectric Formed by Dry Oxidation of Thermal Nitride

We have proposed an approach to grow thin oxynitride gate dielectric (equivalent oxide with the capability for preventing boron penetration. In this method, oxynitride is formed by dry oxidation of ultrathin thermal nitride grown in low pressure. The secondary ion mass spectroscopy profile indicates that its nitrogen peak is located at the gate dielectric surface and possesses concentrations as high as Transmission electron spectroscopy analysis shows that this oxynitride has uniform thickness and a very smooth interface with the Si substrate. Surface roughness is also evaluated by atomic force spectroscopy and exhibits acceptable roughness for device operation. The capability to suppress boron penetration is further proven by the flatband voltage shift in C-V measurement. In addition, its practicality for device operation is also characterized by electrical performances for gate dielectric integrity and reliability. Most importantly, this process is not complicated and fully compatible with existent ultralarge scale integration technology. © 2003 The Electrochemical Society. All rights reserved.

Functionalized One-Dimensional Wires and their Interconnections

Many device scientists believe that current Ultra Large Scale Integration (ULSI) technology will face technical and economic difficulties in further miniaturization. It has been proposed that 1-dimensional (1-D) transistors with connecting wires and three-dimensionally stacked structures may replace current field effect transistors with planar integration structures. We propose a new scheme to fabricate and integrate 1-D active devices. As a first step, we show the way to form 1-D wires with spatially variable electronic structures and the way to characterize them.

Novel Highly Conductive Silver-Tungsten Thin Films Electroless Deposited from Benzoate Solution for Microelectronic Applications

In this study we present the results of electroless deposition of silver-tungsten (Ag-W) films on suitable for applications in microelectronics and ultralarge-scale integration technology. The thin-film composition and resistivity was studied as a function of the bath formulation. The optimal parameters (temperature, pH) and composition of aqueous solution for the deposition of Ag-W thin films with minimum resistivity were defined. It was shown that elevated temperature of the deposition bath results in impairment of solution stability and causes the Ag-W film resistivity to increase. Thin-film morphology was studied using scanning electron microscopy and optical microscopy. Ag-W electrical properties as a function of film deposition rate, composition, and structure were discussed. Novel Ag-W layers with improved properties, such as electrical resistivity and surface coverage, are presented in this work. The highest concentration of tungsten in Ag-W deposits was with oxygen concentration about 4 atom %. Resistivity of 150 nm thick Ag-W films reaches a value of and it is for layers thinner than 60 nm. These films can be applied as both barrier and capping layers for corrosion protection of Ag. The possibility of reducing Ag-W film resistivity using vacuum annealing is demonstrated. © 2003 The Electrochemical Society. All rights reserved.

Effect of in-situ plasma cleaning on the crystalline quality of silicon homoepitaxial films

Low temperature processing, which includes in-situ cleaning and epitaxial deposition, is not only important for future silicon ULSI (Ultra Large Scale Integration) technology but also for silicon based heterostructures. Low temperature processing cannot volatilize or dissolve the surface contaminants by heating the substrate, as was accomplished in the traditional high temperature epitaxial growth. In this study, electron cyclotron resonance (ECR) hydrogen plasma was used and films were deposited thermally at a low temperature. The epitaxial films, which were deposited in our chemical vapor deposition systems, immediately after the insitu cleaning processes were characterized by cross-sectional transmission electron microscopy, etc. The role of a hydrogen ion in the in-situ cleaning was clarified by investigating the cleaning efficiencies for a variety of conditions. Process variables such as cleaning temperature and d.c. bias were investigated, and the d.c bias turned out to play a crucial role in low-temperature in-situ cleaning processes. Also, the effect of the in-situ cleaning temperature on the cleaning efficiency was investigated and discussed.