Ultra-high Integration Research Articles

Conformal oxide coating of carbon nanotubes

The International Roadmap for Ferroelectric Memories requires three-dimensional integration of high-dielectric materials onto metal interconnects or bottom electrodes by 2010. Here, we demonstrate the possibility of conformally coating carbon nanotubes with high-dielectric oxide as a first step toward ultrahigh integration density of three-dimensional ferroelectric random access memories.

LIQUID SOURCE MISTED CHEMICAL DEPOSITION PROCESS OF THREE-DIMENSIONAL NANO-FERROELECTRICS WITH SUBSTRATE HEATING

ABSTRACT A modification of liquid source misted chemical deposition process (LSMCD) with heating mist and substrate has developed, and this enabled to control mist penetrability and fluidity on sidewalls of three-dimensional structures and ensure step coverage. A modified LSMCD process allowed a combinatorial approach of Pb(Zr,Ti)O3 (PZT) thin films and carbon nanotubes (CNTs) toward ultrahigh integration density of ferroelectric random access memories (FeRAMs). The CNTs templates were survived during the crystallization process of deposited PZT film onto CNTs annealed at 650°C in oxygen ambient due to a matter of minute process, so that the thermal budget is quite small. The modified LSMCD process opens up the possibility to realize the nanoscale capacitor structure of ferroelectric PZT film with CNTs electrodes toward ultrahigh integration density FeRAMs.

Nanoscale capacitors based on metal-insulator-carbon nanotube-metal structures

We report the fabrication process and the electrical characteristics of a nanocapacitor structure using metal-insulator-carbon nanotube-metal layers. The structure shows high capacitance and the possibility of ultrahigh integration density due to the unique nanotube structure. Nanoscale and high-aspect-ratio patterns are achieved by electron beam lithography for the fabrication of these vertical nanostructures. This structure can be substituted for capacitors based on the silicon pillar structure in dynamic random access memory or as a nanoscale capacitor for various nanoelectronic devices.

Nanophotonic Computing Based on Optical Near-Field Interactions between Quantum Dots

SUMMARY We approach nanophotonic computing on the basis of op-tical near-field interactions between quantum dots. A table lookup, ormatrix-vector multiplication, architecture is proposed. As fundamentalfunctionality, a data summation mechanism and digital-to-analog conver-sion are experimentally demonstrated using CuCl quantum dots. Owing tothe diffraction-limit-free nature of nanophotonics, these architectures canachieve ultrahigh density integration compared to conventional bulky opti-cal systems, as well as low power dissipation. key words: nanophotonics, optical signal processing, optical near-field,information processing, nanophotonic computing 1. Introduction To accommodate the continuously growing amount of datatraffic in communication systems [1], optics is expected tofurther enhance the overall system performance by perform-ing certain functional behavior [2]. In this regard, so-calledall-optical packet switching has been thoroughly investi-gated. Also, the application of optical features, such as par-allelism, in computing systems has been investigated sincethe 1970s [3],[4]. However, many technological difficultiesremain to be overcome; one problem is the poor integrabilityof the hardware due to the diffraction limit of light, whichis much larger than the gate width in VLSI circuits. Thisresults in relatively bulky hardware configurations.Nanophotonics, on the other hand, is free from thediffraction limit since it is based on local electromagnetic in-teractions between a few nanometric particles, such as quan-tum dots (QDs), via optical near-fields [5]. From an archi-tectural perspective, this drastically changes the fundamen-tal design rules of optical functional systems.In this paper, we propose a nanophotonic comput-ing architecture composed of table-lookup operations, asschematically shown in Fig.1. A large amount of lookup-table (routing table) data can be recorded by configuring the

Single level integrated packaging modules for high performance electronic systems

In this paper, we studied a novel packaging scenario that aims to integrate or eliminate the existing multilevel packaging hierarchies toward single level integration. This new approach is an extension of VLSI technology where standard IC processes were pursued in the whole fabrication sequence. Main benefits include very high performance, ultra high density, mixed-signal integration, and inexpensive. Several key technologies such as chip assembly and planarization were developed. A feasible fabrication procedure for single level integration has been established. Demonstrating modules were presented. Interconnect structures, signal and power distribution, and electrical performance were studied theoretically and experimentally for GHz off-chip operating. Properties of signal propagation and coupling from chip to chip were investigated both in frequency domain and in time domain by simulations and by high frequency measurements. The studies show that the new modules are capable of several Gb/s/pin data rate for off-chip communications. Besides, some design guidelines for best performance are obtained through the work.

ATM in B-ISDN communication systems and VLSI realization

The Asynchronous Transfer Mode (ATM) is considered to be a key technology for B-ISDN. This paper discusses VLSI trends and how VLSI's can be applied to realize ATM switching node systems for B-ISDN. Implementing a practical ATM node system will require the development of technologies such as high-throughput ATM switch LSI's with up to 10 Gb/s capacity and SDH termination technology based on optical fiber transmission. An ATM traffic-handling mechanism with Quality of Service (QoS) controls such as ATM layer performance monitoring, virtual channel handling, usage parameter control, and VP shaping requires several hundred thousand logic gates and several megabytes of high-speed static RAM; VLSI's must be introduced if such mechanisms are to be implemented. ATM node system architecture is based on design principles of a building-block-type structure and hierarchical multiplexing. The basic ATM call handling module, the AHM, is composed mainly of a line termination block and a self-routing switch block; we analyzed this module from the viewpoint of the amount of hardware it requires. Finally, future ATM node systems are discussed on the basis of 0.2-/spl mu/m VLSI development trends and hardware requirements such as the need for ultrahigh integration of logic gate with memory, multichip modules, and low power dissipation technology. >