Ultraclean Si Research Articles

Atomic Level Chemical and Structural Properties of Silicon Surface and Initial Stages of Oxidation

This work aims to summarize previous results reported in literature on atomic level properties of the wet chemically treated hydrogen-terminated silicon surfaces and of the Si oxidation, in comparison to a model system of ultraclean Si surfaces prepared in ultrahigh vacuum (UHV) conditions. A literature review shows that a proper wet chemical treatment of Si(111) provides an atomically smooth, high-quality surface, similar to the model template obtained in UHV conditions after high temperature heating. However, it seems that Si(111) is an exception among semiconductor surfaces concerning the effects of wet chemistry. Although the insulator films grown by the atomic layer deposition (ALD) have replaced the thermal oxide of SiO2 in many applications, still an intermediate SiO2 layer is formed and often grown intentionally beneath the ALD film to improve the device performance. However, a detailed atomic structure of the SiO2/Si interface is still debatable, which might be due to differences in atomic level smoothness of the used Si(100) starting surfaces.

Growth of large aspect ratio AuAg bimetallic nanowires on Si(110) substrate

Large aspect ratio bimetallic nanowire structures comprise potential applications in areas such as higher catalytic activity and surface Raman enhancement spectroscopy (SERS) substrates. By using the highly anisotropic ultra-clean Si(110) surface and with initial growth of sub monolayer (ML) Ag on such surface, a high aspect ratio AuAg bimetallic nanostructures can be formed. We report on the formation of large aspect ratio (>7.2±0.8) AuAg nanowires on ultra-clean Si(110) surfaces using 0.5 ML Ag followed by 3.0 ML Au using molecular beam epitaxy (MBE) at a growth temperature of 300°C. Under similar growth conditions without pre-deposition of Ag and only with deposition of 3.0 ML of Au consequences smaller aspect ratio (2.1±0.1) monometallic Au nanostructures. The enhancement in aspect ratio of the nanostructures is attributed to the formation of one dimensional Ag layer (prior to Au growth) and Au-Ag bimetallic intermixing at elevated temperature. Considering deposition of 3.0 ML Au, a regime of substrate temperature≈270–330°C is found to be optimum to growth some of high aspect ratio (>25.0) AuAg nanowires as well. Exterior of this regime, at lower temperature due to low mobility of the ad-atoms and at higher temperature due to probable inter-diffusion of Ag, such extremely high aspect ratio AuAg nanowires found to be infrequent to grow. For growth at substrate temperature 300°C, mean aspect ratio of the AuAg nanostructures is gradually increased in accordance with Au thickness up to 3.0 ML due to preferential accumulation of ad-atoms (Au, Ag) along Si〈11¯0〉 and thereafter reduces for adequate accumulation along Si〈001〉.

Effects of Hydroxyethyl Cellulose and Colloidal Silica Abrasive on the Hydrophilicity of Polished Si Wafer Surfaces

Final polishing processes are important to produce a clean surface in Si semiconductor wafers. Final polishing is carried out using a slurry that typically comprises colloidal silica, alkaline and a water-soluble polymer. Hydroxyethyl cellulose (HEC) has been widely used as a water-soluble polymer to impart hydrophilic properties to the polished wafer surface in order to reduce defects. In this study, we examined the effects of HEC concentration on the hydrophilicity of the polished wafer surface. We show correlations between the free HEC concentration in slurry liquid phase, friction during polishing, and hydrophilicity of the polished wafer surface. Furthermore, we show that the residual silica abrasive on the wafer enhances its hydrophilicity. These results show that HEC in the slurry not only acts as a hydrophilizing agent but also as an adsorptive medium between the wafer and silica. Silica has a highly hydrophilic surface owing to the presence of Si-O− groups on its surface. Therefore, a highly hydrophilic surface of polished wafer is achieved by adsorptive HEC as well as silica adsorbed on the wafer, bound by HEC. This mechanism is useful to develop new final polishing slurries to produce ultra-clean Si wafers.

Disorder-free localization around the conduction band edge of crossing and kinked silicon nanowires

We explore ballistic regime quantum transport characteristics of oxide-embedded crossing and kinked silicon nanowires (NWs) within a large-scale empirical pseudopotential electronic structure framework, coupled to the Kubo-Greenwood transport analysis. A real-space wave function study is undertaken and the outcomes are interpreted together with the findings of ballistic transport calculations. This reveals that ballistic transport edge lies tens to hundreds of millielectron volts above the lowest unoccupied molecular orbital, with a substantial number of localized states appearing in between, as well as above the former. We show that these localized states are not due to the oxide interface, but rather core silicon-derived. They manifest the wave nature of electrons brought to foreground by the reflections originating from NW junctions and bends. Hence, we show that the crossings and kinks of even ultraclean Si NWs possess a conduction band tail without a recourse to atomistic disorder.

Shape transformation of Si1−xGex structures on ultra clean Si(5 5 7) and Si(5 5 12) surfaces

We report growth of Ge nano/micro structures on ultra clean, high vicinal silicon surfaces of Si(5 5 7) and Si(5 5 12) under two substrate heating conditions: direct current (DC) and radiative heating (RH). These were grown under ultra high vacuum conditions while keeping the substrate at a temperature of 600°C. The results for 10 monolayer (ML) and 12 ML thick Ge deposited on the above surfaces show spherical island structures for RH conditions while aligned trapezoidal structures were observed under DC conditions of heating. We find that the longer side of trapezoid structures are along <11̄0> irrespective of DC current direction. In the case of 10 ML Ge deposited on Si (5 5 7), elongated SixGe1−x nanostructures with an average length of ≈300 nm and a length/width ratio of ≈3.3 have been formed along the step edges. Under similar conditions for 10 ML Ge growth on Si(5 5 12), we found aligned SixGe1−x trapezoidal microstructures of length ≈6.25 μm and an aspect ratio of ≈3.0. Scanning transmission electron microscopy (STEM) measurements showed the mixing of Ge and Si at the interface and throughout the over-layer. Detailed electron microscopy studies (scanning electron microscopy (SEM) and STEM) reveal the structural aspects of these microstructures.

DC heating induced shape transformation of Ge structures on ultraclean Si(5 5 12)surfaces

We report the growth of Ge nanostructures and microstructures on ultraclean, highvicinal angle silicon surfaces and show that self-assembled growth at optimumthickness of the overlayer leads to interesting shape transformations, namely fromnanoparticle to trapezoidal structures, at higher thickness values. Thin films ofGe of varying thickness from 3 to 12 ML were grown under ultrahigh vacuumconditions on a Si(5 5 12) substrate while keeping the substrate at a temperature of600 °C. The substrate heating was achieved by two methods: (i) by heating a filamentunder the substrate (radiative heating, RH) and (ii) by passing direct currentthrough the samples in three directions (perpendicular, parallel and at45° to the direction of the substrate). We find irregular, more spherical-like island structuresunder RH conditions. The shape transformations have been found under DCheating conditions and for Ge deposition more than 8 ML thick. The longer sides ofthe trapezoid structures are found to be along irrespective of the DC current direction. We also show the absence of such a shapetransformation in the case of Ge deposition on Si(111) substrates. Scanning transmissionelectron microscopy measurements suggested the mixing of Ge and Si. This has been confirmedwith a quantitative estimation of the intermixing using Rutherford backscatteringspectrometry (RBS) measurements. The role of DC heating in the formation of alignedstructures is discussed. Although the RBS simulations show the presence of a possibleSiOx layer, under the experimental conditions of the present study, the oxide layer would notplay a role in determining the formation of the various structures that were reported here.

Oxidation of Step Edges onSi(001)−c(4×2)

The initial oxidation process of the ultraclean Si(001)-c(4x2) surface is studied using scanning tunneling microscopy at low temperature. At the early stage of oxygen adsorption, reactions with Si atoms at SB steps are dominant over those at terraces by more than 2 orders of magnitude, and they proceed in two distinct stages to high oxidation states. Guided by the ab initio calculations, the oxidation structures at each stage are proposed. The extreme reactivity of the step edge is due to the presence of rebonded adatoms with dangling bonds and weak rebonds, and their proximity allows the formation of -Si-O- chain structures along the step edge, unlike those on the Si(111) surface.

Alternative NH[sub 4]F/HCl solution for ultraclean Si(001) surface

Ultraclean silicon surface after wet cleaning is extremely crucial in critical steps such as pregate clean in the next generation of electronic devices. Metallic contamination has an adverse effect on device characteristics and must be controlled as low as possible, typically less than 1010 atoms/cm2. A new solution was developed for wet chemical cleaning of silicon, which was investigated by using scanning tunneling microscope, inductively coupled plasma mass spectrometer and total reflection x-ray fluorescence spectrometry. It was found that NH4F with HCl diluted with deionized water resulted in the least surface roughness (0.16±0.02 nm) on silicon and metallic impurities adhered to the silicon surface compared to diluted HF. With the new solution, Cu impurity, the major metallic contamination, was suppressed to less than 2×109 atoms/cm2. Other metallic impurities such as Ca, Fe, Zn, and Ti on the silicon surface were at level of 1010 atoms/cm2, which were lower than that treated by diluted HF. The resu...

Growth kinetics and electrical characteristics of ultra-thin pyrogenic silicon oxide

Ultra-thin (3 to 6.5 nm) SiO 2 layers are grown on ultra-clean Si surfaces by thermal oxidation in steam at low temperatures (650–700°C). The growth characteristics in the ultra-thin oxide thickness region are examined and it is shown that uniform oxide layers can be grown reproducible. It is demonstrated that these pyrogenic SiO 2 layers grown on ultra-clean Si surfaces have a high yield and a reliability that is at least comparable with those of dry oxides.

Kapitza phonon transmission from clean H‐silicon(111) surfaces into liquid helium

AbstractWe have studied the phonon transmission from ultraclean Si(111) surfaces into liquid helium by the phonon pulse technique. Reflection experiments and angular resolving transmission experiments were performed to measure the absolute value of the transmission coefficient and its dependence on the phonon emission angle into the solid. Clean samples etched conventionally in dilute HF show a significant anomalous transmission. An additional etch step in highly buffered HF (i.e., NH4F) with a pH‐value of 7.8 reduces the transmission coefficient drastically. Local inhomogeneities of the transmission coefficient caused by the deposition of water molecules on the surface could be visualized by the enhanced transmission. We found that the observed anomalous transmission is caused by mass defects.

Segregation and Removal of Metallic Impurity at Interface of Silicon and Fluorine Etchant

Realization of an ultraclean Si wafer surface is essential for achieving the advanced process in the ultralarge scale integrated production such as low‐temperature process and high selectivity. An ultraclean wafer surface is defined as a surface completely free from particles, organic impurities, metallic impurities, native oxide, surface microroughness, and adsorbed impurities. Since metallic impurities, one of the above contaminants, cause fatal damage to device characteristics, metallic impurities on the wafer surface need to be suppressed at least below 1010 atom/cm2 which is the level of the detection limit of total reflection x‐ray fluorescence. The current dry processes such as ion implantation and reactive ion etching cause metallic contamination of 1012 to 1013 atom/cm2. In order to remove the metallic contamination, the wet cleaning process plays an increasingly important role. When organic impurities remain on the wafer surface, native oxide and metallic impurities on the wafer cannot be completely removed. In order to establish an ultraclean wafer surface, therefore, it is crucial to remove organic impurities first of all. The wet cleaning process is the only possible method at present to remove trace organic contaminants on the wafer surface. We have studied the segregation and removal of metallic impurities on the solid/liquid interface between chemicals and various Si wafer surfaces (p, n, p+, n+). We tested several chemicals employed in the process to remove oxide on the Si surface. Metals featuring high electronegativity (such as Cu) are directly adsorbed on the bare Si surface while taking electrons away from the Si surface. It has been found that these metals are hard to remove. We used Cu as being representative of metals to be directly adsorbed on the bare Si surface and studied its segregation and removal on the solid/liquid interface between Si wafer and chemicals to keep the Si surface bare such as DHF, , and BHF. It has been found that Cu ion in DHF adheres on every Si wafer surface that we used in our study (p, n, p+, n+), especially on the n+‐Si surface. The solution is found to be effective in removing metals featuring high electronegativity such as Cu from the p‐Si and n‐Si wafers. Even when the solution has Cu ions at the concentration of 1 ppm, this solution is found effective in cleaning the wafer. In the case of the n+‐Si and p+‐Si wafers, however, their surfaces get contaminated with Cu when Cu ion of 10 ppb remains in the solution. When BHF is used, Cu in BHF is more likely to contaminate the p‐Si, n‐Si, and p+‐Si wafers but is less likely to contaminate the n+‐Si wafer. It is also revealed that the surfactant added to BHF to improve its wettability onto the Si wafer is effective in preventing Cu precipitation onto the p‐Si, n‐Si, and p+‐Si wafers. This effect of the surfactant, however, is not observed on the n+‐Si wafer. It is found also that the surface microroughness on the n+‐Si wafer is increased when it is immersed in the solution for 10 min. The etch rate of and BHF on the n+‐Si wafer is found to be much higher than that on the other Si wafers. In order to suppress the metallic contamination on every type of Si surface below , the metallic concentration in ultrapure water and high‐purity DHF which is employed at the final stage of the cleaning process must be lowered below the part per trillion level. cleaning is effective in removing metallic impurities on the p and n surfaces which are required to feature extremely high cleanliness level, such as the wafer surface before gate oxidation. The solution, however, degrades surface roughness on the substrate with the n+ and p+surfaces. In order to remove metallic impurities on these surfaces, there is no choice at present but to use the cleaning and the cleaning.

Raman Scattering Spectrum Along a Bevel Etched GaAs on Si, Tem Study and GaAs P-I-N Photodetector on Si

ABSTRACTRaman scattering is measured along a bevel etched GaAs epitaxial film grown on Si by molecular beam epitaxial (MBE). From the correlation length profile of Raman scatteringmost dislocation lines are confined in the 2000Å regions close to the interface. The strain profile calculated from the Raman peak shift shows that about 0.6% compressive strain exists near the interface because of lattice mismatch. However, as one moves away from the interface, the compressive strain is gradually counterbalanced by thermal expansion. Transmission electron microscope (TEM) studies of the local dislocation image and properties show that an ultra clean Si surface is essential for dislocation confinement. From high resolution TEM, we find that the distance between dislocations at the interface is nonuniform, varying from 50Å to 125Å with an average distance at 81Å. Finally, a GaAs p-i-n photodetector on Si substrate is fabricated. Even though a normal photoresponse curve is obtained, the high dark current (50nA) and relatively low responsivity (0.01A/W) show that the material quality needs to be further improved to make a minority carrier vertical transition device.