ULSI DRAM Research Articles

A review of ULSI failure analysis techniques for DRAMs 1. Defect localization and verification

In this paper defect localization and verification procedures for ULSI DRAMs are described. The analytical process can be grouped into three subsequent phases: component based, die based and local techniques. Beginning with non-destructive localization methods on component level, such as X-ray and scanning acoustic microscopy (SAM), subsequent depackaging of the component enables more extensive electrical probing and physical defect localization at die level. The techniques applied at that level are liquid crystal, optical beam-induced current (OBIC), photo emission microscopy (PEM) and focused ion beam (FIB) to narrow down the failing area. The final fail location is determined after subsequent unlayering steps. Electrical microprobing and FIB techniques are utilized to verify the precisely localized fail within the previously determined area.

Metal Organic Chemical Vapor Deposition of (Ba,Sr)RuO 3 Conductive Oxide Film for (Ba,Sr)TiO 3

(Ba,Sr)RuO 3 films have been tailored as an electrode for (Ba,Sr)TiO 3 which is a promising material for the high dielectric in ULSI DRAM. In this study, BSR conductive oxide film was deposited on 4-inch Si-wafer by metal organic chemical vapor deposition (MOCVD) using single cocktail source for the practical device application. Liquid delivery system (LDS) and vaporization cell were utilized for the delivery and vaporization of single cocktail source, respectively. The source feeding rate was controlled by liquid mass flow controller(LMFC). Ba(METHD) 2 , Sr(METHD) 2 , Ru(METHD) 3 precursors and solvent [n-butylacetate(C 6 H 12 O 2 )] were mixed for single coctail source. Among the various deposition parameters, control of the oxygen flow rate turned out to be crucial for determining the phase formation, resistivity, and the composition ratio of (Ba,Sr)RuO 3 films. Highly (110)-textured (Ba,Sr)RuO 3 film was obtained when Ar/O 2 ratio was 100/300sccm with the source flow rate of 0.075sccm. Oxygen annealing of (Ba,Sr)RuO 3 films enhanced the properties of the films without changing the (110) texture, and the resistivity of the resulted film was 2440 w z cm.

Metal Organic Chemical Vapor Deposition of (Ba,Sr)RuO 3 Conductive Oxide Film for (Ba,Sr)TiO 3

(Ba,Sr)RuO 3 films have been tailored as an electrode for (Ba,Sr)TiO 3 which is a promising material for the high dielectric in ULSI DRAM. In this study, BSR conductive oxide film was deposited on 4-inch Si-wafer by metal organic chemical vapor deposition (MOCVD) using single cocktail source for the practical device application. Liquid delivery system (LDS) and vaporization cell were utilized for the delivery and vaporization of single cocktail source, respectively. The source feeding rate was controlled by liquid mass flow controller(LMFC). Ba(METHD) 2 , Sr(METHD) 2 , Ru(METHD) 3 precursors and solvent [n-butylacetate(C 6 H 12 O 2 )] were mixed for single coctail source. Among the various deposition parameters, control of the oxygen flow rate turned out to be crucial for determining the phase formation, resistivity, and the composition ratio of (Ba,Sr)RuO 3 films. Highly (110)-textured (Ba,Sr)RuO 3 film was obtained when Ar/O 2 ratio was 100/300sccm with the source flow rate of 0.075sccm. Oxygen annealing of (Ba,Sr)RuO 3 films enhanced the properties of the films without changing the (110) texture, and the resistivity of the resulted film was 2440 w z cm.

ChemInform Abstract: (Pb,Sr)TiO3 Thin Films for a ULSI DRAM Capacitor Prepared by Liquid Source Misted Chemical Deposition.

AbstractChemInform is a weekly Abstracting Service, delivering concise information at a glance that was extracted from about 100 leading journals. To access a ChemInform Abstract of an article which was published elsewhere, please select a “Full Text” option. The original article is trackable via the “References” option.

Environmental Ozone Effect on the Growth of Hemispherical Grained Silicon for ULSI DRAM Stacked Capacitor

Hemispherical grained silicon (HSG Si) is a state-of-the-art method used to increase the surface area of the bottom electrode in an ultralarge-scale integration dynamic random access memory (ULSI DRAM) stacked capacitor. Since contaminants affect the formation and growth of HSG Si, the control of surface cleanliness on amorphous Si of the bottom electrode is crucial. The most critical contaminant is native oxide which forms when amorphous Si surface of the bottom electrode is exposed to air. Native oxide growth is mainly influenced by airborne ozone In this work, it is shown that the native oxide grows linearly with exposure time to Also we show that there is a high growth rate of native oxide at a high concentration of and that HSG-Si formation in is related to crystalline quality, morphology, and reflectivity. Electrical characteristics of HSG Si are evaluated with respective conditions and a variation of capacitance is observed. Additionally, an in situ precleaning process followed by the growth of HSG Si under vacuum and implementation of chemical filters are proposed in order to control © 2001 The Electrochemical Society. All rights reserved.

(Pb,Sr)TiO3 Thin Films for a ULSI DRAM Capacitor Prepared by Liquid Source Misted Chemical Deposition

(Pb,Sr)TiO3 (PST) thin films have been successfully grown on Pt-coated Si(100) wafers by the liquid source misted chemical deposition method. The PST thin film has high crystallinity, a smooth surface, and uniform elemental composition. Electrical measurements revealed the PST thin film has a high dielectric constant, low dielectric loss, and good insulating properties. These results indicate that the PST thin film is a promising material for a ULSI DRAM capacitor and other microelectronic device applications.

Studies on structural and electrical properties of barium strontium titanate thin films developed by metallo-organic decomposition

Thin films of barium strontium titanate (BST) including BaTiO 3 and SrTiO 3 end members were deposited using the metallo-organic decomposition (MOD) technique. Processing parameters such as nonstoichiometry, annealing temperature and time, film thickness and doping concentration were correlated with the structural and electrical properties of the films. A random polycrystalline structure was observed for all MOD films under the processing conditions in this study. The microstructures of the films showed multi-grains structure through the film thickness. A dielectric constant of 563 was observed for (Ba 0.7Sr 0.3)TiO 3 films rapid thermal annealed at 750°C for 60 s. The dielectric constant increased with annealing temperature and film thickness, while the dielectric constant could reach the bulk values for thicknesses as thin as ∼ 0.3 μm. Nonstoichiometry and doping in the films resulted in a lowering of the dielectric constant. For near-stoichiometric films, a small dielectric dispersion obeying the Curie-von Schweidler type dielectric response was observed. This behavior may be attributed to the presence of the high density of disordered grain boundaries. All MOD processed films showed trap-distributed space-charge limited conduction (SCLC) behavior with slope of ∼ 7.5–10 regardless of the chemistry and processing parameter due to the presence of grain boundaries through the film thickness. The grain boundaries masked the effect of donor-doping, so that all films showed distributed-trap SCLC behavior without discrete-traps. Donor-doping could significantly improve the time-dependent dielectric breakdown behavior of BST thin films, mostly likely due to the lower oxygen vacancy concentration resulted from donor-doping. From the results of charge storage density, leakage current and time-dependent dielectric breakdown behavior, BST thin films are found to be promising candidates for 64 and 256 Mb ULSI DRAM applications.

Characteristics of PECVD grown tungsten nitride films as diffusion barrier layers for ULSI DRAM applications

We have developed tungsten nitride (W-Nitride) films grown by plasma enhanced chemical vapor deposition (PECVD) for barrier material applications in ultra large scale integration DRAM devices. As-deposited W-Nitride films show an amorphous structure, which transforms into crystalline, β-W2N and α-W phases upon annealing at 800°C. The resistivity of the as-deposited films grown at the NH3/WF6 gas flow ratio of 1 is about 160 μω-cm, which decreases to 50 μω-cm after an rapid thermal annealing treatment at 800°C. In the contact holes with the size of 0.35 μm and aspect ratio of 3.5, the bottom step coverage of the tungsten nitride films is about 60%, which is about three times higher than that of collimated-TiN films. We obtained contact resistance and leakage current with the tungsten nitride barrier layer comparable to those with conventional collimated TiN films. The contact resistance and leakage current are stable upon thermal stressing at 450°C up to 48 h.

Characterization of MOCVD Pt electrode for ferroelectric thin films

Abstract Platinum thin films were deposited by low pressure chemical vapor deposition (LPMOCVD) on SiO2/Si and (Ba, Sr)TiO3/Pt/SiO2/Si substrates using Pt-hexafluoroacetylacetonate at various deposition temperatures. The shiny mirror-like Pt thin films of a high electrical conductivity were obtained, when the deposition temperature is between 325°C and 350°C, whereas above 375°C Pt thin films showed rough surface as well as poor adhesion property to oxide substrate. Pt thin films had a good step coverage of 90%. The results indicate that LPMOCVD Pt thin films can be applied for the top electrode of high dielectric thin film, which is thought to be one of the best candidate materials for a capacitor of ULSI DRAM.

Fabrication and Electrical Characterization of Pt/(Ba,Sr)TiO3/Pt Capacitors for Ultralarge-Scale Integrated Dynamic Random Access Memory Applications

Pt/(Ba, Sr)TiO3/Pt capacitors are fabricated using DC and RF magnetron sputtering processes on thermally oxidized silicon wafers for ultralarge scale integrated dynamic random access memory (ULSI DRAM) applications. (Ba,Sr)TiO3 (BST) thin film deposited at 640°C to 20 nm thickness shows an equivalent SiO2 thickness (t oxeq) of 0.35 nm and a leakage current density, measured at an applied voltage of 1.5 V, of about 100 nA/cm2. t oxeq of the BST film and leakage current density are further decreased to 0.24 nm and 40 nA/cm2, respectively, by postannealing at 750°C after fabrication of the top electrode.

Dielectric breakdown in high-ε films for ulsi DRAMs: III. Leakage current precursors and electrodes

Abstract A somewhat qualitative review of leakage currents J(V,t) in perovskite oxides is presented. It is stressed that space-charge-limited currents (SCLCs) are not alternatives to ionic conduction, Schottky emission, Poole-Frenkel, or Fowler-Nordheim tunneling, but can occur whenever currents due to any of those mechanisms reach a certain threshold and are no longer limited by the details of the metal electrode-ferroelectric interface. Standard metal-semiconductor band models that exclude surface states fail qualitatively to account for the experimental dependences of leakage currents and breakdown voltages on electrode work function; the correct model is metal-n-p-n-metal, with surface donor-state trapping. A discussion of conduction properties in these materials is presented from an ionic conductor viewpoint.

Leakage and interface engineering in titanate thin films for non-volatile ferroelectric memory and ulsi drams

Abstract The leakage behavior of Pb(Zr,Ti)O3 PZT and (Ba,Sr)TiO3 (BST) thin films has been studied. The leakage behavior is dependent upon the bottom electrode. PZT films on RuO2 bottom electrodes display a large leakage, predominantly ohmic in behavior, which we have shown to be PZT microstructure-controlled. The leakage of PZT and BST films on Pt display Schottky emission characteristics which is controlled by the film/electrode interface. In the case of PZT films, we have shown that several methods can be utilized to successfully lower the RuO2/PZT/RuO2 system leakage, while retaining the long term performance. These methods include pre-annealing of RuO2 bottom electrode prior to PZT film deposition; addition of buffer layer between RuO2 and PZT film; and PZT film growth via in-situ ion beam sputter-deposition.

The effect of deposition temperature on the material and electrical properties of PZT thin films for ULSI DRAM applications

Abstract The effects of deposition temperature on the properties of thin films of sputtered lead-zirconate-titanate (PZT) have been studied for ULSI DRAM storage capacitor dielectric applications. The films were deposited by reactive dc magnetron sputtering from a multi-component target. The grain size for the films deposited at 400°C was found to be less than 1000 A, while it was ∼ 10–30 μm for films deposited at 200°C. Small grain-sized material is desirable since it leads to better cell-to-cell uniformity in terms of charge storage capacity and other electrical and reliability properties. The optimum lead compensation was found to increase as the deposition temperature (T dep) increased. Leakage current density stays fairly constant as T dep is varied. As-deposited films, with a deposition temperature of 500°C, were rich in the perovskite phase and showed a high charge storage density of 11.2 μC/cm2 and a low leakage current density of 5.1 × 10−7 A/cm2 (both at 1.5 V). This implies the possibility of e...

Electrode-dielectric interface in thin-film DRAMs for ULSI

Abstract Mechanisms of leakage currents and d.c. breakdown are reviewed for several high-dielectric films in prototype use for ULSI DRAMs, including barium strontium titanate, lead zirconate titanate, and proprietary materials, with special emphasis upon electrode interface phenomena. The early theory of Von Hippel is reviewed, and attention is paid to the modified boundary conditions to the thermal breakdown equation given below for the finite dimensions of capacitors in real ULSI DRAMs (EB is the breakdown field):

Deposition of barium strontium titanate and strontium titanate via Liquid Source Chemical Vapor Deposition

Abstract Liquid Source Chemical Vapor Deposition (LSCVD) involves the use of sub-saturated aerosols of specially designed metallorganic precursors suitable for multicomponent oxide deposition in vacuum at room temperature. Materials of interest for ULSI DRAMs, such as Ba(1−x)SrxTiO3 and SrTiO3 show uniform deposition with microstructures optimized for step-coverage and small capacitor geometries. Electrical characteristics indicate capacitance densities of around 25–30 fF/um2 and leakages in the order of 10−8 A/um2. A review of these results and the LSCVD technique will be presented.

Trends in the development of ULSI DRAM capacitors

Abstract DRAM manufacturers face a tremendous challenge to keep the DRAM cell capacitance constant from generation to generation. The 256 Mb DRAM will certainly represent the last DRAM generation to use the standard storage dielectric materials consisting of silicon dioxide and silicon nitride. These materials cannot be shrunk further, and the capacitor area cannot be kept constant in a manufacturable cell. The most promising approach to keep cell capacitance constant in future DRAM generations, beyond 256 Mb, is to develop and integrate high dielectric constant materials.

Dielectric breakdown in high-ε films for ULSI DRAMs: II. barium-strontium titanate ceramics

Abstract We present a study of breakdown fields in BaxSr1−xTiO3 ceramics as functions of thickness, temperature, applied voltage ramp rate, electrode material and cross-sectional area. The data show evidence of Zener-like breakdown mechanisms. The d.c. leakage currents at voltages below breakdown are dominated by tunneling injection and image forces at low voltages (≤3 V), Schottky behavior at intermediate voltages V a (3 V ≤ V a ≤ 6 V; 150 kV/cm ≤ E ≤ 300 kV/cm), and Fowler-Nordheim tunneling at high voltages; it is shown that both the Schottky emission regime and the ultimate breakdown arise from inter-grain effects rather than the BST/electrode interface, in accord with the theory of Neumann and Arlt and of Waser and Klee. In contrast to PbZrxTi1−xO3 (PZT), which displays avalanche breakdown and space-charge limited d.c. leakage currents at normal 5 V silicon IC voltages, BST exhibits Schottky-dominated leakage currents in this 5 V regime, and is dominated by Fowler-Nordheim tunneling in its breakdown ...

Characterization of Tantalum Oxide Thin Film and its Electrodes for DRAM's Capacitor Application

Thermal stability, microstructure and electrical property of molybdenum nitride film were studied for application of ULSI's DRAM capacitor electrode and copper diffusion barrier. Phase transformation from Mo to γ-Mo 2 N was observed at 20% N2/(Ar+N 2 ) flow ratio and γ-Mo 2 N and Δ-MoN phases coexisted at 50% N 2 flow ratio. γ-Mo 2 N film was found to crystallize at 400°C. Amorphous γ-Mo 2 N deposited at 300 °C remained stable upon 750 °C heat treatment. Breakdown strengths of Y -Mo 2 N/Ta 2 O&/Si MOS capacitor before and after 850 °C annealing were 2.4 MV/cm and 1.85 MV/cm at 1×10 -6 A/cm 2 , respectively. After 850 °C annealing, dielectric constant of Ta 2 Os film decreased to 19.

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

For future ULSI DRAMs beyond the 256 Mb generation, several circuit techniques and memory cell structures have been proposed to meet the requirement of high performance at low voltage. These solutions frequently involve complicated processing steps and/or the ultimate limitations of current Si-MOS devices. DRAM on silicon on insulator (SOI) substrate is a more simple solution to the problem. Thin-film SOI structures with isolation by implanted oxygen (SIMOX) process are under investigation for SRAM and logic. A SOI-DRAM test device with 100 nm thick SOI film has been fabricated in 0.5 /spl mu/m CMOS/SIMOX technology. With this 64 kb SOI-DRAM the bit-line to memory cell capacitance ratio Cb/Cs is reduced by 25% compared with the reference bulk-Si DRAM, because of the decreased junction capacitance. RAS access time tRAC is 70 ns at 2.7 VVcc, as fast as the equivalent bulk-Si device at 4 VVcc. The clock timing in this DRAM is not optimized, so access time should improve with well-tuned clocks. The boosted-level generator with body-contact structure enhances the upper Vcc margin and the reduced body-effect of sense-amplifier transistors improves the lower Vcc margin. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. >

The Effects of La Concentration on the Properties of PLT Thin Films: From the Perspective of Dram Applications

ABSTRACTWe have studied the effects of La concentration on the dielectric and ferroelectric properties of lead lanthanum titanate (PLT) thin films by using sol-gel method. Both the dielectric and ferroelectric properties were greatly affected by the La concentration. The dielectric constants of the films varied from 340 to 870 with varying La concentration in the range from 15 to 33 mol%. Hysteresis loop became slimmer with the increase of La concentration from 15 to 28 mol% and a little fatter again with the increase of La concentration from 28 to 33 mol%. Among the films investigated in this research, PLT(28) thin film showed the best dielectric properties for the application to the dielectrics of ULSI DRAM's. At the frequency of 100 Hz, the dielectric constant and the loss tangent of PLT(28) thin film were 940 and 0.08, respectively. Its leakage current density at 1.5×10 V/cm was 1×10−6 A/cm2. The comparison between the simulated and the experimental curves for the switching transient characteristics showed that PLT(28) thin film behaved like normal dielectrics.