UMOS Structure Research Articles

Practical superjunction MOSFET device performance under given process thermal cycles

The performance of specific on-state resistance (Ron,sp) versus breakdown voltage (Vbr) of a superjunction power MOSFET device is constrained by the quality of its sidewall junctions formed by neighbouring p and n columns in the drift region. The p–n junction quality, which is inevitably affected by the inter-column dopant diffusion in practice, will limit the Ron,sp–Vbr device performance if no compensation measure is taken. A detailed study of the influence of sidewall junction quality on performance at various column widths under given thermal process conditions was carried out through process and device simulations. The study discovers the practical optimal performance of superjunction (SJ) DMOS and UMOS structures under the influence of dopant inter-column diffusion. Analysis of the phenomenon shows that the degradation of the breakdown voltage is caused by the p and n column charge imbalance. Practical SJ performance equations, which model the influence reasonably well, are derived in the paper. These equations can be used to predict the practical performance of an SJ device under given thermal conditions, which in turn guides us to the compensation measures required to achieve better performance.

Remote PECVD Oxide Utilized in U-MOS Structures and Different MOSFETs on SiC

Remote PECVD Oxide Utilized in U-MOS Structures and Different MOSFETs on SiC

High-voltage accumulation-layer UMOSFET's in 4H-SiC

A novel silicon carbide UMOSFET structure is reported. This device incorporates two new features: a self-aligned p-type implantation in the bottom of the trench that reduces the electric field in the trench oxide, and an n-type epilayer under the p-base to promote lateral current spreading into the drift region. This UMOS structure is capable of supporting the full blocking voltage of the pn junction while keeping the electric field in the gate oxide below 4 MV/cm. An accumulation channel is formed on the sidewalls of the trench by epigrowth, and the gate oxide is produced by a polysilicon oxidation process, resulting in a uniform oxide thickness over both the sidewalls and bottom of the trench. The fabricated 4H-SiC devices have a blocking voltage of 1400 V (10 /spl mu/m drift region), a specific on-resistance of 15.7 m/spl Omega/-cm/sup 2/ at room temperature, and a gate oxide field of 3 MV/cm.

The behavior of very high current density power MOSFETs

A new and complete description of the current carrying mechanisms of a power MOSFET is presented. This is aimed at clarifying the relatively complex behavior of such devices operating at high current densities, with particular reference to the drain-voltage dependence associated with quasi-saturation. This physical insight provides an elegant method of comparing the relative merits of the DMOS and UMOS structures.

Bulk charge effects in VLSI MOSFET's

An analysis of the relative magnitudes of the bulk charge for three MOSFET structures suitable for VLSI devices, such as NMOS (normal), VMOS (V slot) and UMOS (U slot), is carried out. It is shown that even for the same channel design (i.e. channel length, doping, source/drain junction depth, and oxide thickness), the amount of bulk charge and hence the threshold voltage can be significantly different for the three structures. This effect becomes more important with decreasing channel length, and increasing source to substrate bias. Further, for a given channel length, the bulk charge and hence the threshold voltage of an NMOS decreases with increasing source/drain junction depth. However, for the VMOS and UMOS structures, the bulk charge as well as the threshold voltage do not depend on the junction depth of the source/drain diffusion. An expression is also derived for the bulk charge of UMOS transistors valid for both short and long channels.

The characteristic studies of VMOS and UMOS

Abstract Under the same process conditions in the conventional diffusion and anisotropic etching technology, short channel MOST with V-shape and U-shape arc fabricated under the same substrate conditions by the standard photolithographical technology. The short channel effect in which the threshold voltage and transconductance vary with the channel length is measured for both VMOS and UMOS structures. Detailed comparisons between both structures are made, and a simple physical interpretation is given