Practical superjunction MOSFET device performance under given process thermal cycles

Abstract

The performance of specific on-state resistance (Ron,sp) versus breakdown voltage (Vbr) of a superjunction power MOSFET device is constrained by the quality of its sidewall junctions formed by neighbouring p and n columns in the drift region. The p–n junction quality, which is inevitably affected by the inter-column dopant diffusion in practice, will limit the Ron,sp–Vbr device performance if no compensation measure is taken. A detailed study of the influence of sidewall junction quality on performance at various column widths under given thermal process conditions was carried out through process and device simulations. The study discovers the practical optimal performance of superjunction (SJ) DMOS and UMOS structures under the influence of dopant inter-column diffusion. Analysis of the phenomenon shows that the degradation of the breakdown voltage is caused by the p and n column charge imbalance. Practical SJ performance equations, which model the influence reasonably well, are derived in the paper. These equations can be used to predict the practical performance of an SJ device under given thermal conditions, which in turn guides us to the compensation measures required to achieve better performance.