Two-step Time-to-digital Converter Research Articles

A Low-Power Sensing System of VEGF Concentration With Noise Reduction Using Subsampling Technique for Cancer Diagnosis

This paper presents a monolithic low-power sensing system for early cancer detection. The system uses a CMOS MEMS capacitive transducer with a gold interdigitated electrode (IDE) and DNA aptamers to sense the concentration of vascular endothelial growth factor (VEGF). When the DNA aptamer is immobilized with the VEGF sensor, it generates an electric double-layer capacitance. The low-noise front-end circuits amplify this capacitance change and convert the signal into the frequency domain. To solve the wide input dynamic range and reduce power consumption, a two-step time-to-digital converter (TDC) is utilized. The proposed sub-sampling (SS) technique provides a higher conversion gain to reject noise interference and overcome the increase in noise floor introduced from the decoder due to lower supply voltage. The sub-sampling delay-locked loop (SSDLL), combined with the calibration circuit, enhances TDC linearity and noise performance while preventing calibration noise from degrading conversion accuracy. Finally, the time-based information is converted into digital codes with high power efficiency for early cancer analysis. The system is fabricated in TSMC 0.35 μm MEMS CMOS process with electroplated gold. Measurement results show that the power consumption of the readout circuit and the overall system is only 18 μW and 60.65 μW, respectively. The proposed system improves jitter by 49% and achieves 0.725 mV/pg-mL sensitivity.

PLL Fractional Spur’s Impact on FSK Spectrum and a Synthesizable ADPLL for a Bluetooth Transmitter

In this work, we present an open-source fully-synthesizable fractional-N all-digital phase-locked loop (ADPLL) designed for a Bluetooth low-energy (BLE) transmitter (TX) along with a semi-analytical model of the PLL fractional spur’s impact on the BLE output spectrum. Based on the model and the BLE specification for spur emission, a requirement for the PLL fractional spurs is derived. To meet the derived spectral mask by reducing the fractional spurs, a novel synthesizable two-step time to digital converter (TSTDC) that employs embedded TDC (EMBTDC) as coarse and Vernier delay-line TDC (DLTDC) as fine TDC is proposed. We also present a digital calibration scheme to compensate for the nonlinearity induced by the place-and-route (P&R) tool. The PLL is fabricated in 12-nm FinFET and demonstrated in a BLE-TX. The measured BLE transmissions satisfy the standard requirements thanks to the reduced fractional spurs. In a standalone PLL mode, the proposed TSTDC and calibration scheme reduced the fractional spurs by 14.3 dB compared to only using an EMBTDC in near-integer <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$</tex-math> </inline-formula> operation. The PLL supports a frequency range of 1.8–2.7 GHz and consumes 3.91 mW at 2.4006 GHz achieving figure of merit (FoM) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 220.7 dB in fractional-N mode with a 40 MHz reference, occupying an area of 0.063 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . A highly automated design flow is used for the PLL to lower the barrier for new developers and reduce the porting cost.

Multievent Histogramming TDC With Pre–Post Weighted Histogramming Filter for CMOS LiDAR Sensors

In this study, we have proposed a CMOS light detection and ranging (LiDAR) sensor with high immunity for background noise (BGN) and inter-LiDAR interference (IF). To mitigate pileup distortions that cause signal loss due to large BGN, we implemented multievent weighted histogramming time-to-digital converter (TDC) with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times4$ </tex-math></inline-formula> macro-pixels. The 11-bit two-step TDC and mixed-signal accumulator (MA) were utilized to implement histogramming with area efficiency. To overcome the limited dynamic range of histogram accumulation while preserving the maximum detectable range (MDR), a pre–post weighted histogram filter was implemented to detect only time-correlated time-of-flight (TOF) out of BGN from both sunlight and increased dark noise while enhancing sensitivity through higher excess voltage of single-photon avalanche diodes (SPADs). In addition, the infinite IF canceling (IIC) scheme that employs pulse-position modulation and time-difference modulation was designed to be compatible with the pre–post weighted histogram filter. For the IIC, the ON-chip SPAD-based random number generator provides a random code. A theoretical analysis of LiDAR performance such as MDR was introduced to prove the effectiveness of the pre-post weighted histogram filter. The fabricated sensor demonstrated 8.08-cm accuracy for a range of 32 m under high BGN (105-klx sunlight and 48.72-kcps dark-count rate with increased excess bias voltage) through the pre–post weighted histogram filter and IF immunity through the IIC scheme.

A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques

This article presents a low power-supplied 13-bit 20-MS/s time-to-digital converter (TDC)-assisted successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the voltage-to-time converter (VTC) and TDC realize an inherent process, voltage, and temperature (PVT) robustness by inner tracking, thus inducing no extra power and circuit overheads. The voltage-domain and time-domain speed-enhanced techniques accelerate the first- and second-stage ADC conversions under a low power supply, respectively. Furthermore, in cooperation with a detect-and-skip switching scheme in the SAR ADC and an offset bit-shifting scheme in the two-step TDC, the ADC achieves linearity of 13 bit. The prototype ADC was fabricated in a 65-nm CMOS process with a 0.6-V power supply, achieving a 71.0-dB signal-to-noise and distortion ratio (SNDR) and an 89.5-dB spurious-free dynamic range with a Nyquist input at 20 MS/s, while exhibiting a Schreier figure-of-merit (FoM) of 181.9 dB. The ADC presents a sub-1-dB SNDR drop across a temperature range of −50 to 90 °C and ±5% power-supply variation.

A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL

This paper presents a new fast-lock all-digital delay-locked loop (DLL) for next-generation memory devices such as DDR5 SDRAMs. The proposed DLL utilizes a new two-step time-to-digital converter (TDC)-based phase detecting and tracking scheme that results in a fast lock time of less than seven clock cycles. Unlike previous TDC-based DLLs, there is an advantage of having a fast lock time regardless of the long-replica clock buffer delay in the DRAM DLL. Implemented in a 65 nm CMOS process, the proposed digital DLL has a wide operating frequency range of 1.65–7.0 GHz and occupies an area of only 0.021 mm2. The DLL dissipates only 7.1 mW from a 1.0 V supply at 7 GHz, and the effective peak-to-peak (p–p) jitter of the output clock is about 4.55 ps at 7 GHz.

A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique.

Herein, we present a low-power cyclic Vernier two-step time-to-digital converter (TDC) that achieves a wide input range with good linearity. Since traditional approaches require a large area or high power to achieve an input range >300 ns, we solve this problem by proposing a simple yet efficient TDC suitable for time-of-flight (TOF) sensors. In previous studies using the cyclic structure, the effect of startup time on the linearity of the TDC is not described. Thus, the achievable linearity has been limited when the TDC is used for applications requiring a high input range. We solve this problem by using a simple yet effective technique to compensate. The proposed technique is realized using (1) digitally-controlled oscillators (DCOs) that have dual frequency control and matched startup time; (2) an alignment detector that performs startup time correction by proper timing control; and (3) a fully symmetric arbiter that precisely detects the instant of edge alignment. To achieve a fine resolution for the cyclic Vernier TDC, we design two closely-matched DCOs with dual frequency control. The alignment detector performs the critical task of cancelling startup time via timing control. The detector is delay-compensated by using a dummy to provide matched loading for the two DCOs. To enhance the detection speed under low power, a current-reuse approach is employed for the arbiter. The TDC is fabricated using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in a compact chip area of 0.028 mm2. Measured results show a dynamic range of 355 ns and a resolution of 377 ps. When the result is applied for TOF sensing, it corresponds to a distance range of 53.2 m and a resolution of 5.65 cm. Over a relatively large input range, good linearity is achieved, which is indicated by a DNL of 0.28 LSBrms and an INL of 0.96 LSBrms. The result corresponds to root mean square (RMS) error distance of 5.42 cm. The result is achieved by consuming a relatively low power of 0.65 mW.

Low‐power TDC scheme using DLL‐based gray counter for infrared imagers

A low-power time-to-digital converter (TDC) scheme for column-level single-slope analogue-to-digital converters for infrared imager is presented. This scheme greatly improves the TDC's timing precision with a novel 3-bit fine gray counter, which makes use of multi-phase clocks from a delay-lock-loop. Aimed for 384 × 288 array size uncooled infrared imager with 17 μm pixel pitch, the TDC circuits have been developed and simulated employing 0.18 μm CMOS technology. Compared with conventional two-step TDC methods, this method saves more chip area and reduces the sampling power consumption by >50%, and also eliminates the coarse-fine inconsistency problem with a simulated ±0.1 least-significant-bit differential non-linearity performance.

A hybrid time-to-digital converter based on residual time extraction and amplification

This paper presents a novel hybrid time-to-digital converter (TDC) for high resolution and wide range time measurement, where a two-stage TDC cooperates with a two-step TDC. First the input time is roughly converted by a coarse-fine two-stage TDC to guarantee wide dynamic range and small quantization error. Then the residual time from the previous conversion is obtained by an extraction circuit and further quantified by a two-step TDC for ultra fine resolution, where the extracted residue is linearly enlarged by a time amplifier (TA), followed by adopting a tapped delay line with original gate delay resolution for measurement. The TA is regulated by delay-locked-loop (DLL) to keep its gain stable under process, voltage and temperature variations. Using full-custom approach, a test chip was designed and implemented in TSMC 0.35-μm CMOS process. With an input reference clock of 100MHz, the proposed 13-bit hybrid TDC achieves a resolution of 320ps, a full range of 2.55μs and a single-shot precision of 0.73 LSB. The DNL is less than ±0.68 LSB and INL is within −1.23 LSB to 1.19 LSB.

Time-of-Arrival Measurement Using Adaptive CMOS IR-UWB Range Finder With Scalable Resolution

This paper introduces an adaptive CMOS impulse-radio ultra-wideband (IR-UWB) range finder with scalable resolution for localization applications and presents a brief demonstration of its operation. The distance resolution of the proposed range finder can be adapted to the ranging environment using a two-step time-to-digital converter (TDC) with scalable delay cells. Using the scalable time resolution of the TDC, the proposed range finder can control its maximum detectable distance and range resolution without any change in hardware. The proposed CMOS IR-UWB range finder has been implemented with a 0.11- $\mu\text{m}$ process; the effective areas of the transmitter and receiver are 0.065 mm2 and 0.27 mm2, respectively. The range finder has a range 8 m, with 2.9 mm scalable resolution. The power consumptions of the transmitter and receiver are 1.5 mW and 42 mW, respectively.

A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors.

This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within −Tclk~+Tclk. A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration.

A 10-Bit Column-Parallel Single Slope ADC Based on Two-Step TDC with Error Calibration for CMOS Image Sensors

This paper presents a 10-bit column-parallel single slope analog-to-digital converter (SS ADC) with a two-step time-to-digital converter (TDC) to overcome the long conversion time problem in conventional SS ADC for high-speed CMOS image sensors (CIS). The time interval proportional to the input signal is generated by a ramp generator and a comparator, which is digitized by a two-step TDC consisting of coarse and fine conversions to achieve a high-precision time-interval measurement. To mitigate the impact of propagation delay mismatch, a calibration circuit is also proposed to calibrate the delay skew within -T/2 to T/2. The proposed ADC is designed in 0.18 μm CMOS process. The power dissipation of each column circuit is 232 μW at supply voltages of 3.3 V for the analog circuits and 1.8 V for the digital blocks. The post simulation results indicate that the ADC achieves a SNDR of 60.89 dB (9.82 ENOB) and a SFDR of 79.98 dB at a conversion rate of 2 MS/s after calibration, while the SNDR and SFDR are limited to 41.52 dB and 67.64 dB, respectively before calibration. The differential nonlinearity (DNL) and integral nonlinearity (INL) without calibration are +15.80/-15.29 LSB and +1.68/-15.34 LSB while they are reduced down to +0.75/-0.25 LSB and +0.76/-0.78 LSB with the proposed calibration.