Low‐power TDC scheme using DLL‐based gray counter for infrared imagers

Abstract

A low-power time-to-digital converter (TDC) scheme for column-level single-slope analogue-to-digital converters for infrared imager is presented. This scheme greatly improves the TDC's timing precision with a novel 3-bit fine gray counter, which makes use of multi-phase clocks from a delay-lock-loop. Aimed for 384 × 288 array size uncooled infrared imager with 17 μm pixel pitch, the TDC circuits have been developed and simulated employing 0.18 μm CMOS technology. Compared with conventional two-step TDC methods, this method saves more chip area and reduces the sampling power consumption by >50%, and also eliminates the coarse-fine inconsistency problem with a simulated ±0.1 least-significant-bit differential non-linearity performance.