Abstract
In this paper, a pipeline Time-to-Digital Converter (TDC) is presented. The TDC consists of clock circuit, pulse generator, three 2.5-bit/stage TDC, a 3-bit delay-line TDC and digital error correction circuit, the final output code is 9-bit, the 2.5-bit/stage TDC consists of time-register, sub-TDC, sub-DTC and time amplifier. A time register is implemented to stores time information, a pulse-train time amplifier is adopted to achieve accurate gain and wide input liner range. The TDC is designed in 0.18μm CMOS technology, the area of the core circuit is 415μm×217μm, the simulation results show that the resolution is 4.62ps and the dynamic range is 0∼2348ps under 50MS/s sampling rate.
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