Two-stage Opamp Research Articles

Enhancing the design of a two-stage CMOS operational amplifier utilising the Bat Algorithm

ABSTRACT The increasing demand for high-performance two-stage CMOS Op-Amps in electronic, communications, and biomedical applications necessitates their operation with wide bandwidth, high voltage gain, and low power consumption. By leveraging the Bat Algorithm global search and local exploration capabilities, the study demonstrates a significant improvement in the amplifier’s overall performance. This design of a two-stage CMOS Op-Amp using 0.18 µm TSMC technology, powered by a ± 1.8 V supply voltage. The simulation outcomes were gathered using the PSPICE software (version 17.4). These design strategies prove highly efficient, achieving high gain, high frequency, and low power consumption. Additionally, the paper showcases the execution and simulation results of a two-stage CMOS Op-Amp based on the Bat Algorithm, utilising MATLAB for this purpose. The employment of the BA results in substantial enhancements in performance metrics. Specifically, the Unity Gain Bandwidth sees a doubling in its value, the voltage gain rises by 20%, power consumption falls by 39.1%, and the Common Mode Rejection Ratio improves by 20% compared to a two-stage CMOS Op-Amp designed without the BA. The findings underscore the BA potency as a robust optimisation method for boosting the performance of a two-stage CMOS Op-Amp.

Analysis of Two Stage CMOS Operational Amplifier in 90nm CMOS Technology

Abstract: Operational amplifier circuits are used in computation, instrumentation and other applications. Precision op-amps previously used in instrumentation are now-a-days being used in industrial and automotive applications. Hence, there always exists a need for better precision op-amps. It should operate under a wide temperature range. Nowadays, due to the industry trend of applying standard process technologies to implement both analog circuits and digital circuits on the same chip, Complementary Metal-Oxide Semiconductor (CMOS) technology has become dominant over bipolar technology for analog circuit design in a mixed-signal system. Two-stage Op-Amp is one of the most commonly used Op-Amp architectures. In this work an operational amplifier based on CMOS is presented whose input depends on its bias currents which is 20µA and designed using 180nm and 90nm technologies. In sub-threshold region due to unique behavior of the MOS transistors not only allows a designer to work at low voltages and it also allows operating at low input bias currents. Most CMOS Op-Amps are designed for specific on-chip applications and are only required to drive capacitive loads of a few pf. In this proposed work, design of a two stage fully differential CMOS operational amplifier is presented and simulations are carried out in 180nm and 90nm technologies for various parameters. The simulation is to be carried out using Cadence Virtuoso Tool.

Folded Cascode Operational Amplifier Design Utilizing 0.25 µm CMOS Technology

A one-stage Folded Cascode Operational Amplifier with the self-biasing scheme for the PMOS differential input stage is designed by using LTspice simulator and the designing procedure is described. This folded op amp will have a high Common-mode input range (ICMR) and a high maximum voltage output thereby high gain. The LTspice simulation results correlate very well with the hand calculations obtained theoretical values. All the MOSFETs are kept in saturation to ensure high open loop gain. Then, a two-stage op amp circuit has been designed by assuming Zero (z)= 10 GB, and phase margin (PM= 68o). The obtained result of the output gain for this design was Avo= 91 dB, indicating that the design has a high gain.

Design of low offset voltage in second stage CMOS operational amplifier using 90nm technology

In this paper a low offset voltage; low power and high gain second stage op-amp of differential amplifier along with common source amplifier with compensated capacitor is proposed. The mathematical analysis of two-stage op-amp is elaborated and this work is compared with exiting similar work. The experimental work carried in CADENCE Virtuoso with 0 gpdk090 process technology is used to obtain 60.994 of Phase Margin, 61 dB DC gain and Offset voltage is 2mV. The M/L ratios are selected accordingly where supply voltage and load voltage are fixed at 1.8V and 12pF respectively. The parametric analysis helps, where the values are fixed to get better response.

A High-Speed Fully Differential Telescopic Op-Amp for Active Filter Designs in V2X Applications

In this paper, an ultra-wideband fully differential two-stage telescopic 65-nm CMOS op-amp is presented, which uses low-voltage design techniques such as level shifter circuits and low-voltage cascode current mirrors. The designed op-amp consists of two stages. While the telescopic first stage provides high speed and low swing, the second stage provides high gain and large swing. Common-mode feedback circuits (CMFB), which contain five transistors OTA and sensing resistors, are used to set the first-stage output to a known value. The designed two-stage telescopic operational amplifier has 41.04[Formula: see text]dB lower frequency gain, 1.81[Formula: see text]GHz gain-bandwidth product (GBW) and 51.9∘ phase margin under 5[Formula: see text]pF load capacitance. The design consumes a total current of 11.9[Formula: see text]mA from a 1.2-V supply voltage. Presented fully differential two-stage telescopic op-amp by using low-voltage design techniques is suitable for active filter in vehicle-to-everything (V2X) applications with 120[Formula: see text][Formula: see text]m[Formula: see text]m layout area.

Ultra-Wide Bandwidth Fully Differential CMOS Opamp with a Novel Bandwidth Extension Technique for SoC Active Filter Applications

An ultra-wide bandwidth fully differential two-stage 65[Formula: see text]nm CMOS operational amplifier (Opamp) is presented, which uses a novel bandwidth extension technique called “pole duplication”. This technique is based on relocating the dominant pole with the same location with a non-dominant pole and adjusting 3-dB frequency and stability with a compensation network. Simulation results show that the proposed Opamp has 103[Formula: see text]MHz 3-dB bandwidth with a 2[Formula: see text]pF load capacitor. It consumes 9[Formula: see text]mA current from 1.2-V supply. Transition frequency of 2.4[Formula: see text]GHz and a gain of 29[Formula: see text]dB is accomplished. A 2[Formula: see text]pF load capacitance can be driven at a phase margin of [Formula: see text]. The suggested pole duplication technique is used to achieve higher 3-dB cut-off frequencies by adjusting the load capacitor. Fully differential two-stage Opamp is presented, which uses a novel bandwidth extension technique, is suitable for SoC active filter applications with 40[Formula: see text][Formula: see text]m layout area and ultra-wide 3-dB bandwidth.

Design of TFET based Op-Amp and CCII for low voltage and low power applications

ABSTRACT This paper presents design of an ultra-low-power two-stage Op-Amp and Second-generation current conveyor (CCII) using gm/ technique for portable applications like biomedical instruments, wireless sensor networks (WSNs), etc. The designed circuits are based on 20 m Tunnel Field-Effect Transistor (TFET). The circuits use a single power supply of 0.9 V and provide improvements in many areas when compared with Carbon Nanotube FET (CNTFET) based circuits and existing TFET-based circuits. The simulation set up in HSPICE, provide very low-power consumption for the same performanceand provide much better performance for the same power consumption when compared with existing circuits. In the case of TFET-based Op-Amp, for the power consumption of 47.1 W, the GBW and open-loop DC gain are 5.12 MHz and 75.9 dB, respectively. While for the power consumption of 107.1 W, the GBW and open-loop DC gain are 9.01 MHz and 74.9 dB, respectively. In case of TFET-based CCII, for the power consumption of 82.3 W, the 3-dB BW for Voltage and Current transfer gains are 700 MHz and 135 MHz, respectively. While for the power consumption of 173 W, the 3-dB BW for Voltage and Current transfer gains are 1.12 GHz and 226 MHz respectively.

COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing

This paper presents a new method to automate the sizing of analog circuits. The method emulates the manual design procedure. The sizing task is formulated as a constraint programming problem. Two new algorithms are introduced: First, a hierarchical structural analysis of functional blocks that automatically sets up the analytical equations for the sizing. And second, a heuristic to guide the branching process of a constraint programming solver. We achieve a reproduction of the manual proceeding of designers and at the same time an automation of the set-up of the design problem, reducing the set-up effort to seconds. The method is primarily designed for operational amplifiers. More than 20 circuits, including different variants of two-stage, folded-cascode, telescopic and symmetrical op-amps, are considered at this time. This paper presents a runtime comparison of the newly developed branching heuristic with a generic branching heuristic on 20 different circuits. Furthermore, sizing results for a two-stage op-amp with transistors in weak inversion and a folded-cascode op-amp with common-mode feedback circuit are presented to show the effectiveness of the approach.

Development of a broad band AC power amplifier for real time turbulence feedback control experiment in the Saskatchewan Torus-modified (STOR-M) tokamak.

A gated oscillating power amplifier has been developed for high frequency biasing and real time turbulent feedback experiments in the Saskatchewan Torus-modified tokamak. This oscillator is capable of providing a peak to peak oscillating output voltage of around ±60 V with a current around 30 A within the frequency band 1 kHz-50 kHz without any distortions. The overall output power is amplified by a two-stage metal oxide semiconductor field-effect transistor power op-amp as well as nine identical push-pull amplifiers in the final stages. The power amplifier input signal, collected from the plasma floating potential during the tokamak discharge, is optically isolated from the tokamak vessel ground. The filtered floating potential fluctuations with a band width of 5 kHz-40 kHz were amplified and fed to an electrode inserted into the plasma edge to study the response of the plasma turbulence. We observe that magnetic fluctuations are suppressed due to real time feedback of the floating potential.

Sensitivity Analysis of the UTBSOI Transistor based Two-Stage Operational Amplifiers

In the nanoscale domain, the MOSFETs are prone to various physical effects due to their shorter channel region known as short-channel effects (SCE). The researchers have proposed an advanced structure of MOSFET known as the ultrathinbody silicon-on-insulator (UTBSOI) to overcome the limitations of SCEs. The UTBSOI is a type of double-gate (DG) MOSFET having superior controllability of gates over the shorter channel region. Nowadays, the UTBSOI MOSFETs can be adopted in the circuit simulators through the use of a device model named BSIM-IMG. The BSIM-IMG has made it possible for the circuit designers to simulate any UTBSOI based analog blocks like operational amplifiers (opamp). The performance parameters of an opamp are very much sensitive to any perturbation in size (W/L) of the constituent MOSFETs, that may cause a drastic change in the output. In this paper, the sensitivity analysis procedure has been proposed for the CMOS and UTBSOI based two-stage opamps as the function of perturbation in W/L. In addition to this, an algorithm has also been presented to do the same. From the simulation results, it is observed that the sensitivity of the UTBSOI based opamp (UTBSOI-opamp) is larger than that of CMOS based opamp (CMOS-opamp).

A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application

In this brief, a dual-supply two-stage op-amp is proposed for a 12-b 1 GS/s pipeline ADC, which is composed of a low-voltage supply pre-amplifier and a high-voltage supply amplifier. Its closed-loop bandwidth reaches to 5.2 GHz, and the phase margin is larger than 60°. The closed-loop amplifier can settle to 99.95% accuracy within 230 ps, which satisfies the harsh requirements of the first-stage MDAC. The proposed op-amp was employed in a single-channel 12-b 1 GS/s pipeline ADC. The ADC is powered by 1.3 V and the op-amp is powered by dual-supply voltage of 1.3 V and 2.5 V. The ADC fabricated in 65 nm CMOS process consumes 360 mW at 1 GS/s. It achieves an SNDR of 61.9 dB and an SFDR of 72.6 dB with 30 MHz input signal, while maintaining an SNDR > 56.0 dB and SFDR > 69.0 dB in the entire 500 MHz Nyquist band.

Rapid and accurate method for resizing CMOS operational amplifiers

A new method for resizing CMOS operational amplifiers is presented in this paper. The basic idea is to match the operating currents and some small signal conductances of transistors in a circuit by solving the matching equations based on the accurate MOSFET model. The resizing experiments of a two-stage OpAmp for the process migration from a 0.35 µm CMOS technology to a 0.18 µm one have been performed to validate the proposed method. The simulation results show that the method generates the resized circuits with smaller area and almost the same performance at a lower computational cost compared with the existing approaches.

Carbon Nanotube CMOS Analog Circuitry

Carbon nanotube (CNT) field-effect transistors (CNFETs) promise significant energy efficiency benefits versus today's silicon-based FETs. Yet despite this promise, complementary (CMOS) CNFET analog circuitry has never been experimentally demonstrated. Here we show the first reported demonstration of full CNFET CMOS analog circuits. For characterization, we fabricate analog building block circuits: multiple instances of two-stage op-amps. These CNFET CMOS op-amps achieve gain >700 (maximum derivative of output voltage with respect to differential input voltage), operate at a scaled sub-500 mV supply voltage, achieve high linearity (even when operating at these scaled voltages), and are robust over time (minimal drift over >10 000 cycled measurements over 12 h). Additionally, we demonstrate a front-end analog subsystem that integrates a CNFET-based breath sensor with an analog sensor interface circuit (transimpedance amplifier followed by a voltage follower to convert resistance change of the chemoresistive CNFET sensor into a buffered output voltage). These experimental demonstrations are the first reports of the CNFET CMOS analog functionality that is essential for a future CNT CMOS technology.

Evolutionary Computation Based Sizing Technique of Nulling Resistor Compensation Based CMOS Two-Stage Op-Amp Circuit

This article explores the comparative optimizing efficiency between two PSO variants, namely, Craziness based PSO (CRPSO) and PSO with an Aging Leader and Challengers (ALC-PSO) for the design of nulling resistor compensation based CMOS two-stage op-amp circuit. The concept of PSO is simple and it replicates the nature of bird flocking. As compared with Genetic algorithm (GA), PSO deals with less mathematical operators. Premature convergence and stagnation problem are the two major limitations of PSO technique. CRPSO and ALC-PSO techniques individually have eliminated the disadvantages of the PSO technique. In this article, CRPSO and ALC-PSO are individually employed to optimize the sizes of the MOS transistors to reduce the overall area taken by the circuit while satisfying the design constraints. The results obtained individually from CRPSO and ALC-PSO techniques are validated in SPICE environment. SPICE based simulation results justify that ALC-PSO is much better technique than CRPSO and other formerly reported methods for the design of the afore mentioned circuit in terms of the MOS area, gain and power dissipation etc.

An efficient method of Pareto-optimal front generation for analog circuits

In this paper, an efficient deterministic methodology for generating Pareto-optimal front (PoF) of analog circuits is proposed. The proposed methodology utilizes modified epsilon constraint method along with geometric programming based circuit sizer to determine the Pareto-optimal points (PoPs) of the analog circuits. The generated PoPs are then modeled to generate the PoFs. The efficiency of the proposed methodology and the accuracy of the generated PoF has been verified with respect to that of the commonly used stochastic approach. It is found that to generate PoF having similar spread, the proposed methodology takes only 20 min whereas the stochastic approach takes 60 h. It also has been observed that the accuracy of the generated PoF using the proposed methodology improved by more than 10% with respect to that of the stochastic approach. The proposed methodology has been implemented to generate the PoF of a two-stage Op-Amp, fully differential folded cascode Op-Amp, fully differential single-stage and two-stage Op-Amps. The generated PoFs have been utilized for (1) feasibility checking for a user given specification of an Op-Amp, (2) performance prediction and (3) topology selection of the analog circuit. As per authors’ knowledge, this is the first paper which deals with all the aspects, i.e., generation, modeling and application of the PoF of the analog circuits.

Co-AGSA: An efficient self-adaptive approach for constrained optimization of analog IC based on the shrinking circles technique

This paper aims to take a step forward to enhance the performance of the optimization kernel of electronic design automation (EDA) tools by coping with the existing challenges in the analog circuit sizing problems. For this purpose, a novel co-evolutionary-based optimization approach, called Co-AGSA, is proposed. In the Co-AGSA, a self-adaptive penalty technique based on the concept of the co-evolution model is incorporated into a powerful optimization algorithm, named advanced gravitational search algorithm (AGSA), to efficiently solve more realistic constrained optimization problems. The performance of the Co-AGSA approach is first evaluated by solving three constrained engineering design problems. Then, the optimization capability of the Co-AGSA-based IC sizing tool is validated using three different case studies, i.e., a two-stage op-amp, a folded-cascode op-amp and a two-stage telescopic cascode amplifier, to show the applicability of the proposed approach. The results demonstrate that the Co-AGSA gives better performance compared to other approaches in terms of efficiency, accuracy and robustness.

Development of a Reflectance Photoplethysmogram Based Heart Rate Monitoring Device

This paper presents a method for users to monitor their heart rate conveniently. It becomes necessary for individuals to know their heart rate because of the fact that cardiovascular disease is the leading cause of death in the world, especially in developing countries. Heart rate measurement is an indication of how healthy the heart is. This heart rate monitor (HRM) uses the technique of reflectance photoplethysmography (PPG) to detect the pulse from the fingertip, filter and amplify the pulse using two-stage OP-Amp, count and decodes the pulse with the aid of a microcontroller and display the output in beats per minutes (BPM) on an LCD. The device is easy to use, cheap and portable compared to the expensive ones available that also requires medical expertise. It can be used by athletes and anybody to monitor the state of their heart rate with negligible error.

An enhanced optimization kernel for analog IC design automation using the shrinking circles technique

This paper presents a novel sizing automation tool to improve the efficiency and accuracy of the analog IC design process. A new technique named the “shrinking circles” is proposed to create a balance between the exploration and exploitation capabilities when the optimization algorithm is converging to a possible optimum point. With the help of the shrinking circles concept, an upgraded version of Gravitational Search Algorithm (GSA) named Advanced GSA (AGSA) is proposed to be used as an optimization kernel for our circuit sizing tool. The performance of the proposed AGSA is evaluated over 23 benchmark functions and the results are compared with the standard GSA and Clustered-GSA algorithms. A two-stage op-amp in the 0.35µm CMOS technology is utilized to validate the performance of the proposed sizing tool. The corners analysis is also performed over the obtained solutions to guarantee their robustness against the process and environmental variations. Finally, a statistical study over the final solutions is conducted from the two aspects of quantitative and qualitative analyses.

A new hybrid algorithm for analog ICs optimization based on the shrinking circles technique

This paper presents a novel technique named the Shrinking Circles to enhance the performance of optimization algorithms embedded in automated sizing tools of analog ICs. This technique creates a balance between the exploration and exploitation capabilities when the optimization algorithm is converging to a possible optimum point. With the help of the shrinking circles concept, we upgrade a hybridization version of Gravitational Search Algorithm with Particle Swarm Optimization (Advanced GSA_PSO). Accordingly, a developed tool for the automation of analog ICs sizing is proposed. The performance of this tool is evaluated by two cases: minimizing the power consumption of a two-stage CMOS op-amp and simultaneous minimizing the circuit area and power consumption of a folded-cascode op-amp. In this paper, the corners analysis is also incorporated into the proposed circuit sizing tool based on a straightforward procedure by which this tool not only can obtain the solutions being robust against process, voltage, and temperature (PVT) variations, but also it alleviates the computational burden. Comparisons with available methods show that the proposed tool performs much better in terms of efficiency.

Stability of a Two-Stage Opamp: A New Perspective

ABSTRACTA new insight into the cause of ringing is presented, which is attributed to the inductance created at the input of the second stage of the operational amplifier. This approach has been verified through the simulation results carried out using BSIM 4.3 50 nm technology.