Evolutionary Computation Based Sizing Technique of Nulling Resistor Compensation Based CMOS Two-Stage Op-Amp Circuit

Abstract

This article explores the comparative optimizing efficiency between two PSO variants, namely, Craziness based PSO (CRPSO) and PSO with an Aging Leader and Challengers (ALC-PSO) for the design of nulling resistor compensation based CMOS two-stage op-amp circuit. The concept of PSO is simple and it replicates the nature of bird flocking. As compared with Genetic algorithm (GA), PSO deals with less mathematical operators. Premature convergence and stagnation problem are the two major limitations of PSO technique. CRPSO and ALC-PSO techniques individually have eliminated the disadvantages of the PSO technique. In this article, CRPSO and ALC-PSO are individually employed to optimize the sizes of the MOS transistors to reduce the overall area taken by the circuit while satisfying the design constraints. The results obtained individually from CRPSO and ALC-PSO techniques are validated in SPICE environment. SPICE based simulation results justify that ALC-PSO is much better technique than CRPSO and other formerly reported methods for the design of the afore mentioned circuit in terms of the MOS area, gain and power dissipation etc.