Two-level Networks Research Articles

Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results

Metal-oxide-semiconductor (MOS) logic elements offer advantages over bipolar logic elements, such as smaller size, complexity, and power consumption, as well as more flexibility and versatility. Since MOS is playing a major role in large-scale integration (LSI), synthesis of MOS networks with a large number of variables is very important.

Logic Properties of Unate Discrete and Switching Functions

The total and local unateness of discrete and of switching functions are studied from a theoretical point of view. One shows that the local unateness leads to the concept of hazard-free transition for a discrete function. Unate covers for discrete functions are defined: they are either the smallest unate functions larger than a discrete function, or the largest unate functions smaller than a discrete function. These concepts play a key role in hazard-free design of multiple-valued networks. Three-level types of multiple-valued networks using MIN and MAX gates are presented. These networks improve, from a hazard point of view the well known two-level networks presented by Eichel-berger in the frame of switching theory.

Design of Optimal Two-Level Logic Networks Using Nor, and, Nand, or Gates

A direct approach is recalled for the determination of optimal two-level networks using NAND, AND, NOR, OR gates.

Design of Two-Level Fault-Tolerant Networks

Some new techniques for the synthesis of fault-tolerant two-level combinational networks are presented. Two classes of faults are defined, 1) critical faults and 2) subcritical faults. Critical fauls are the class of faults that cannot be tolerated by any two-level networks. Necessary conditions for synthesis of networks tolerating subcritical faults are developed. As a result it is established that the conditions required for tolerating faults in the logic elements and those required for tolerating faults in the primary inputs are significantly different. Several design techniques are presented and it is shown that if we restrict our class of faults, then certain normally assumed conditions on redundancy can be relaxed. A class of hazards is defined. It is shown that the synthesis of certain hazard-free realizations is equivalent to the fault-tolerant realization, and also an upper bound on the redundancy of the fault-tolerant realization is derived.

Techniques for the design of two-level fault tolerant logic networks: Iowa Univ., Mathematics Dept. Iowa City, USA (April 1972) 31pp

Abstract : A technique for the synthesis of fault-tolerant combinational networks is presented. The novelty of the technique lies in the framework in which the problem is formulated. Necessary conditions for the synthesis of two-level networks tolerating stuck-at type faults are developed. It is shown that there exists a significant difference between the conditions that have to be satisfied for the synthesis of networks in which only internal faults are masked and in which both internal and primary input faults are masked. As a result, it is established that certain normally assumed conditions are too strong. Design techniques are presented for the synthesis of networks tolerating all types of faults except the faults which change the output to the constant function. A class of hazards is defined. It is shown that the synthesis of certain hazard-free realizations is equivalent to the fault-tolerant realization. (Author)

Minimum Two-Level Threslold Gate Realizations

This paper deals with the synthesis of two-level networks of threshold gate logic elements for realization of nonlinearly separable switching functions. The realization obtained contains the minimum number of threshold logic elements possible for a two-level realization. An algorithm based on the tree procedure of Coates and Lewis is developed which can be used to obtain the desired network realization for a given switching function. The function may be incompletely specified.

Detection of Multiple Faults in Combinational Logic Networks

New techniques are presented for generating fault-detection experiments for combinational logic networks. Only single-output functions are considered. Test-covering and test-equivalence relations between networks are defined and these relations are shown to be Instrumental in generating the experiments. The techniques presented provide minimal experiments for detecting multiple faults In two-level networks and provide nearly minimal experiments for most other networks.

Design of Optimal Switching Networks by Integer Programming

The design of optimal logic networks is formulated as integer programming (IP) problems. This formulation has the following advantages over other methods of logic design. 1) General feed-forward networks can be dealt with rather than two-level or three-level networks usually treated in conventional switching theory. 2) Network restrictions such as fan-in and fan-out restrictions are easily incorporated. 3) Various gate types such as NOR, NAND, AND-OR combination, NOR-AND combination, and those gates with NOR-OR dual outputs can be treated. 4) Various objectives such as the number of gates and the number of connections are minimized. 5) Incompletely specified functions can be handled without additional difficulty. 6) The formulation can be extended to multiple-output networks. To solve the resulting IP problems, the implicit enumeration method of integer programming is found to be suitable. An IP code ILLIP (Illinois Integer Programming Code) is implemented based on the implicit enumeration by incorporating some new gimmicks such as pseudounderlining. Then the ILLIP is used to solve the IP problems for logical design by making use of the inherent structure of our problems. Various optimal networks are derived by a computer as follows: optimal NOR networks and optimal NOR-AND networks for all functions of up through three variables, one-bit adders with various gate types, and others. These results indicate the computational feasibility of the integer programming approach.

The Simplification of Multiple-Output Switching Networks Composed of Unilateral Devices

The purpose of this paper is to show that two-level (no more than two gates in cascade) multiple-output switching networks composed of unilateral switching devices such as diodes can be simplified or minimized in much the same manner as single-output networks. This is accomplished by extending the notation and techniques used in the simplification of two-level single-output switching networks to multiple-output switching networks. A simple procedure for identifying multiple-output prime implicants is devised and, as a final result, an algorithm is presented which can be used to minimize the switching network corresponding, to a number (q) of given Boolean expressions of the same variables. This algorithm is based on the Quine rules but has been modified to take advantage of the so-called ``don't care'' conditions which occur because some inputs are forbidden or because some outputs are of no concern. This algorithm can readily be programmed on a digital computer if desired.