Two-dimensional Discrete Cosine Research Articles

Image Fusion Using Pca in Cs Domain

Compressive sampling (CS), also called Compressed Sensing, has generated a tremendous amount of excitement in the image processing community. It provides an alternative to Shannon/Nyquist sampling when the signal under acquisition is known to be sparse or compressible. In this paper, we propose a new efficient image fusion method for compressed sensing imaging. In this method, we calculate the twodimensional discrete cosine transform of multiple input images, these achieved measurements are multiplied with sampling filter, so compressed images are obtained. we take inverse discrete cosine transform of them. Finally, fused image achieves from these results by using PCA fusion method. This approach also is implemented for multi-focus and noisy images. Simulation results show that our method provides promising fusion performance in both visual comparison and comparison using objective measures. Moreover, because this method does not need to recovery process the computational time is decreased very much.

A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers

In this paper, a single compensation formula of adaptive conditional-probability estimator (ACPE) applied to fixed-width Booth multiplier is proposed. Based on the conditional-probability theory, the ACPE can be easily applied to large length Booth multipliers (such as 32-bit or larger) for achieving a higher accuracy performance. To consider the trade-off between accuracy and area cost, the ACPE provides varying column information to adjust the accuracy with respect to system requirements. The 16-bit ACPE Booth multiplier with w = 3 reduces 28.9% silicon area with only 0.39 dB signal-to-noise ratio (SNR) loss when compared with post-truncated (P-T) Booth multiplier. Furthermore, the ACPE Booth multipliers are applied to two-dimensional (2-D) discrete cosine transform (DCT) to evaluate the system performance. Implemented in a TSMC 0.18 CMOS process, the DCT core with ACPE (w = 3) can save 14.3% area cost with only 0.48 dB peak-signal-to-noise-ratio (PSNR) penalty compared to P-T method.

Shared hardware, high throughput implementation of 2D 4 × 4 and 8 × 8 integer transform for H.264/AVC high-profile coders

Two-dimensional discrete cosine transforms are used in the core transformations in all profiles of the H.264/Advanced video coding (AVC) standard. In this paper, implementing the resource sharing of high throughput 4×4 and 8×8 forward and inverse integer transforms for high definition H.264 is presented. It is shown that the 4×4 forward/inverse transform can be obtained from 8×8 forward/inverse transform using selective data input and data arrangement at intermediate stages. Fast 8×8 forward and inverse transform is implemented using matrix decomposition and matrix operation such as Kronecker product and direct sum. The proposed implementation does not require any transpose memory and has a dual clocked pipeline structure. Compared with existing designs, the gate count is reduced by 27.7% in the proposed design. The maximum operating frequency of the proposed system is approx. 1.3GHz, while the throughput is 7G and 18.7G pixels/s for 4×4 and 8×8 forward integer transforms, respectively. The proposed design can be used for real time H.264/AVC high definition processing owing to its high throughput and low hardware cost.

Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias

In this paper, a closed form of compensation function for fixed-width Booth multipliers using generalized probabilistic estimation bias (GPEB) is proposed. Based on the probabilistic estimation from the truncation part, the GPEB circuit can be easily built according to the proposed systematic steps. The GPEB fixed-width multipliers with variable-correction outperform the existing compensation circuits in reducing error. An 8 × 8 GPEB Booth multiplier improves more than 88% on the reduction of absolute average error compared with the traditional direct truncation (D-T) multiplier, and more than 32% area savings is obtained in the GPEB Booth multiplier compared with posttrun cation (P-T) Booth multiplier. By the same power consumption, the GPEB Booth multipliers can achieve higher accuracy than the existing works. Besides, considering power efficiency with accuracy, the proposed GPEB Booth multiplier has the most power-efficiency compared with other methods. Furthermore, the GPEB Booth multipliers are implemented in the circuit of two-dimensional discrete cosine transform (DCT). Compared with traditional Booth multiplier's applications, the proposed 2-D DCT cores can reduce about 18% area cost with the penalty of only 0.8 dB peak signal-to-noise ratio (PSNR). Consequently, the Booth multiplier utilizing area-efficiency, power-efficiency, and high-accuracy is achieved using the proposed GPEB.

Two-Dimensional Discrete Sine Transform and Discrete Cosine Transform Based on Two-Dimensional Multimode Interference Couplers

In this letter, all-optical two-dimensional discrete sine transform and discrete cosine transform (2DDST/DCT) are proposed to be realized on two-dimensional multimode interference (2DMMI) couplers. Similar to the one-dimensional case, the 2DDST/DCT requires only one 2DMMI coupler and a few phase shifters.

Estimation of human red blood cells size using light scattering images

In this paper, a novel method for the estimation of the human Red Blood Cell (RBC) size using light scattering images is presented. The information retrieval process includes, image normalization, a two-dimensional Discrete Cosine Transformation (DCT2) or Wavelet transformation (DWT2), and a Radial Basis Neural Network (RBF-NN) estimates the RBC geometrical properties. The proposed method is evaluated in both regression and identification tasks when three important geometrical properties of the human RBC are estimated using a database of 1575 simulated images generated with the boundary element method. The experimental setup consists of a light beam at 632.8 nm and moving RBCs in a thin glass and additive noise distortion is simulated using white Gaussian noise from 60 to 0 dB SNR. The regression and identification accuracy of actual RBC sizes is estimated using three feature sets, giving a mean error rate less than 1 percent of the actual RBC size, in case of noisy image data at 10 dB SNR or better, and more than 97 percent mean identification rate.

Recognition of handwritten Arabic alphabet via hand motion tracking

This paper proposes an online video-based approach to handwritten Arabic alphabet recognition. Various temporal and spatial feature extraction techniques are introduced. The motion information of the hand movement is projected onto two static accumulated difference images according to the motion directionality . The temporal analysis is followed by two-dimensional discrete cosine transform and Zonal coding or Radon transformation and low pass filtering. The resulting feature vectors are time-independent thus can be classified by a simple classification technique such as K Nearest Neighbor (KNN). The solution is further enhanced by introducing the notion of superclasses where similar classes are grouped together for the purpose of multiresolutional classification. Experimental results indicate an impressive 99% recognition rate on user-dependant mode. To validate the proposed technique, we have conducted a series of experiments using Hidden Markov models (HMM), which is the classical way of classifying data with temporal dependencies. Experimental results revealed that the proposed feature extraction scheme combined with simple KNN yields superior results to those obtained by the classical HMM-based scheme.

Recursive algorithm, architectures and FPGA implementation of the two-dimensional discrete cosine transform

A new recursive algorithm and two types of circuit architectures are presented for the computation of the two-dimensional discrete cosine transform (2D DCT). The new algorithm permits to compute the 2D DCT by a simple procedure of the 1D recursive calculations involving only cosine coefficients. The recursive kernel for the proposed algorithm contains a small number of operations. Also, it requires a smaller number of pre-computed data compared with many of existing algorithms in the same category. The kernel can be easily implemented in a simple circuit block with a short critical delay path. In order to evaluate the performance improvement resulting from the new algorithm, an architecture for the 2D DCT designed by direct mapping from the computation structure of the proposed algorithm has been implemented in an FPGA board. The results show that the reduction of the hardware consumption can easily reach 25% and the clock frequency can increase 17% compared with a system implementing a recently reported 2D DCT recursive algorithm. For a further reduction of the hardware, another architecture has been proposed for the same 2D DCT computation. Using one recursive computation block to perform different functions, this architecture needs only approximately one-half of the hardware that is required in the first architecture, which has been confirmed by an FPGA implementation.

Hybrid Modeling of Intra-DCT Coefficients for Real-Time Video Encoding

The two-dimensional discrete cosine transform (2-D DCT) and its subsequent quantization are widely used in standard video encoders. However, since most DCT coefficients become zeros after quantization, a number of redundant computations are performed. This paper proposes a hybrid statistical model used to predict the zeroquantized DCT (ZQDCT) coefficients for intratransform and to achieve better real-time performance. First, each pixel block at the input of DCT is decomposed into a series of mean values and a residual block. Subsequently, a statistical model based on Gaussian distribution is used to predict the ZQDCT coefficients of the residual block. Then, a sufficient condition under which each quantized coefficient becomes zero is derived from the mean values. Finally, a hybrid model to speed up the DCT and quantization calculations is proposed. Experimental results show that the proposed model can reduce more redundant computations and achieve better real-time performance than the reference in the literature at the cost of negligible video quality degradation. Experiments also show that the proposed model significantly reduces multiplications for DCT and quantization. This is particularly suitable for processors in portable devices where multiplications consume more power than additions. Computational reduction implies longer battery lifetime and energy economy.

A unified framework for image compression and segmentation by using an incremental neural network

This paper presents a novel unified framework for compression and decision making by using artificial neural networks. The proposed framework is applied to medical images like magnetic resonance (MR), computer tomography (CT) head images and ultrasound image. Two artificial neural networks, Kohonen map and incremental self-organizing map (ISOM), are comparatively examined. Compression and decision making processes are simultaneously realized by using artificial neural networks. In the proposed method, the image is first decomposed into blocks of 8 × 8 pixels. Two-dimensional discrete cosine transform (2D-DCT) coefficients are computed for each block. The dimension of the DCT coefficients vectors (codewords) is reduced by low-pass filtering. This way of dimension reduction is known as vector quantization in the compression scheme. Codewords are the feature vectors for the decision making process. It is observed that the proposed method gives higher compression rates with high signal to noise ratio compared to the JPEG standard, and also provides support in decision-making by performing segmentation.

Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties

In this paper, a novel architecture for two-dimensional (2-D) inverse discrete cosine transform (IDCT) is implemented using 90-nm CMOS technology. By exploiting the sparseness property of a 2-D discrete cosine transform (DCT) coefficient matrix and the even and odd symmetry properties of the basis vectors of the one-dimensional (I-D) DCT, the proposed architecture reduces computational complexity and increases a throughput rate effectively. First, we derive a recursion equation from the definition of the 2-D IDCT algorithm and use it to design an efficient 2-D IDCT architecture. The proposed architecture consisting of processing elements is suitable for very-large-scale-integration implementation due to its highly regular and scalable structure for 2-D N /spl times/ N IDCT computations. Based on the derived recursion equation, we show how data How for the outer products scaled by only nonzero 2-D DCT coefficients performs 2-D IDCT naturally with low complexities of the controller and the interconnection. The proposed architecture based on the recursion equation provides optimum balance in both hardware complexity and throughput rate when compared with other 2-D IDCT architectures.

A new time distributed DCT architecture for MPEG-4 hardware reference model

This paper presents the design of a new time distributed architecture (TDA) which outlines the architecture (ISO/IEC JTC1/SC29/WG11 MPEG2002/M8565) submitted to MPEG4 Part9 committee and included in the ISO/IEC JTC1/SC29/WG11 MPEG2002/9115N document. The proposed TDA optimizes the two-dimensional discrete cosine transform (2-D-DCT) architecture performance. It uses a time distribution mechanism to exploit the computational redundancy within the inner product computation module. The application specific requirements of input, output and coefficients word length are met by scheduling the input data. The coefficient matrix uses linear mappings to assign necessary computation to processor elements in both space and time domains. The performance analysis shows performance savings in excess of 96% as compared to the direct implementation and more than 71% as compared to other optimized application specific architectures for DCT.

Direct Recursive Structures for Computing Radix-<tex>$r$</tex>Two-Dimensional DCT/IDCT/DST/IDST

In this paper, new recursive structures for computing radix-r two-dimensional (2-D) discrete cosine transform (DCT) and 2-D inverse DCT (IDCT) are proposed. The 2-D DCT/IDCT are first decomposed into cosine-cosine and sine-sine transforms. Based on indexes of transform bases, the regular pre-addition preprocess is established and the recursive structures for 2-D DCT/IDCT, which can be realized in a second-order infinite-impulse response (IIR) filter, are derived without involving any transposition procedure. For computation of 2-D DCT/IDCT, the recursive loops of the proposed structures are less than that of one-dimensional DCT/IDCT recursive structures, which require data transposition to achieve the so-called row-column approach. With advantages of fewer recursive loops and no transposition, the proposed recursive structures achieve more accurate results and less power consumption than the existed methods. The regular and modular properties are suitable for very large-scale integration (VLSI) implementation. By using similar procedures, the recursive structures for 2-D DST and 2-D IDST are also proposed.

Pel reconstruction on FPGA-augmented TriMedia

This paper presents a TriMedia processor extended with three reconfigurable designs for entropy decoding (ED), inverse quantization (IQ), and two-dimensional (2-D) inverse discrete cosine transform (IDCT), and assesses the performance gain that is provided by such extensions when performing MPEG2-compliant pel reconstruction. We first describe an extension of the TriMedia architecture, which consists of a multiple-context field programmable gate array (FPGA)-based reconfigurable functional unit (RFU), a configuration unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the ED, IQ, and 2-D IDCT tasks, and propose to provide reconfigurable hardware support for a variable-length decoder that can decode two symbols per call (VLD-2), an inverse quantizer that can dequantize four coefficients per call (IQ-4), and an 1-D IDCT (1-D IDCT). The most important aspects concerning the implementation of the FPGA-mapped VLD-2, IQ-4, and 1-D IDCT units, as well as the organization of the software routines calling these FPGA-mapped computing units are outlined. Experimental results indicate that by configuring each of the VLD-2, IQ-4, and 1-D IDCT units on a different FPGA context, and by activating the contexts as needed, the FPGA-augmented TriMedia can perform MPEG2-compliant pel reconstruction with an average speed-up of 1.4/spl times/ over the standard TriMedia.

An Efficient 2-D DCT/IDCT Core Design Using Cyclic Convolution and Adder-Based Realization

This paper proposes an efficient two-dimensional (2-D) discrete cosine and inverse discrete cosine transform (DCT/IDCT) core design. Adopting the row-column decomposition technique for computing 2-D DCT/IDCT, we formulate the one-dimensional (1-D) DCT/IDCT into cyclic convolution by properly arranging the input sequence, optimize the multiplications based on the concept of common subexpression sharing, and carry out the multiplications through carry-save adders (CSAs). Using cyclic convolution is helpful in exploiting the word-level data sharing in computing different DCT/IDCT outputs. Adopting the common subexpression sharing is beneficial to the bit-level data sharing in computing the outputs. As compared with some existing approaches of realizing DCT/IDCT, the proposed approach can save on average 20%/spl sim/33% in the delay-area product (gate-count * time-unit) based on a 0.35-/spl mu/m CMOS technology under the data word-lengths ranging from 16/spl sim/24 b. Besides, we have also proposed an IP generator for designing the 2-D DCT/IDCT based on the proposed approach. It provides a design-automation environment with parameter configurations in designing a 2-D DCT/IDCT core that is suitable for most image and video compression applications.

New Cost-Effective VLSI Implementation of a 2-D Discrete Cosine Transform and Its Inverse

This paper first reviewed the two-dimensional discrete cosine transform (2-D DCT) and inverse DCT (IDCT) architectures. Then a new VLSI architecture, namely the transpose free row column decomposition method (TF-RCDM), for 2-D DCT/IDCT is proposed. The new RCDM architecture replaces the transpose circuits with permutation networks and parallel memory modules. As results, the timing overhead of I/O operations is eliminated and the hardware complexity is largely reduced. An accuracy testing system is designed to find the optimum word-length parameters. Based on the accuracy testing system, the proposed architecture has achieved the smallest word-length among the reported 2-D DCT architectures. Synthesis results showed that with 0.25-/spl mu/m CMOS technology library, the area was about 1.5 mm/sup 2/ and the speed was about 125 MHz.

Fast wave-front reconstruction by solving the Sylvester equation with the alternating direction implicit method

Large degree-of-freedom real-time adaptive optics (AO) control requires reconstruction algorithms that are computationally efficient and readily parallelized for hardware implementation. In particular, we find the wave-front reconstruction for the Hudgin and Fried geometry can be cast into a form of the well-known Sylvester equation using the Kronecker product properties of matrices. We derive the filters and inverse filtering formulas for wave-front reconstruction in two-dimensional (2-D) Discrete Cosine Transform (DCT) domain for these two geometries using the Hadamard product concept of matrices and the principle of separable variables. We introduce a recursive filtering (RF) method for the wave-front reconstruction on an annular aperture, in which, an imbedding step is used to convert an annular-aperture wave-front reconstruction into a squareaperture wave-front reconstruction, and then solving the Hudgin geometry problem on the square aperture. We apply the Alternating Direction Implicit (ADI) method to this imbedding step of the RF algorithm, to efficiently solve the annular-aperture wave-front reconstruction problem at cost of order of the number of degrees of freedom, O(n). Moreover, the ADI method is better suited for parallel implementation and we describe a practical real-time implementation for AO systems of order 3,000 actuators.

Efficient block-based video encoder embedding a Wiener filter for noisy video sequences

Since pre-filtering removes camera noise and improves coding efficiency dramatically, its efficient implementation has been an important issue in video sequence coding. Based on the approximated generalized Wiener filtering and two-dimensional discrete cosine transform (DCT) factorization, this paper introduces a novel pre-filtering scheme that is performed inside a video encoder. The proposed pre-filtering is performed, by scaling the DCT coefficients of original image blocks for intra block coding and those of motion-compensated error blocks for inter block coding, respectively. Even though the pre-filtering operation is embedded in a video encoder, its additional computational complexity is marginal for given signal-to-noise ratio (SNR) estimates, and the overall architecture of the conventional video encoder is maintained. Notwithstanding its simplicity, the proposed pre-filtering scheme gives good filtering and coding performance for noisy video sequences.

Two-dimensional DCT∕IDCT architecture

A fully parallel architecture for the computation of a two-dimensional (2-D) discrete cosine transform (DCT), based on row-column decomposition is presented. It uses the same one-dimensional (1-D) DCT unit for the row and column computations and (N2+N) registers to perform the transposition. It possesses features of regularity and modularity, and is thus well suited for VLSI implementation. It can be used for the computation of either the forward or the inverse 2-D DCT. Each 1-D DCT unit uses N fully parallel vector inner product (VIP) units. The design of the VIP units is based on a systematic design methodology using radix-2n arithmetic, which allows partitioning of the elements of each vector into small groups. Array multipliers without the final adder are used to produce the different partial product terms. This allows a more efficient use of 4:2 compressors for the accumulation of the products in the intermediate stages and reduces the number of accumulators from N to one. Using this procedure, the 2-D DCT architecture requires less than N2 multipliers (in terms of area occupied) and only 2N adders. It can compute a N×N-point DCT at a rate of one complete transform per N cycles after an appropriate initial delay.

RNS-based implementation of 8×8 point 2D-DCT over field-programmable devices

A new implementation of an 8×8 two-dimensional discrete cosine transform (2D-DCT) processor based on the residue number system (RNS) is presented. This architecture makes use of a fast cosine transform algorithm. It is shown that the RNS implementation of the 2D-DCT over field-programmable logic devices leads to a 129% throughput improvement over the equivalent binary system.