Turn-off Time Research Articles

Optical gating characteristic time of measurement with 20 picoseconds resolution for an ultrafast image intensifier

In order to study the optical gating time characteristic of an ultra-fast gated image intensifier, a precision measuring system with 20 ps (picoseconds) trigger jitter is established. The sequential gate images of the image intensifier with a time interval of 20 ps are obtained at 0.125 ns ∼2 ns (nanoseconds) gating electrical pulse modes. These images show that the intensifier has the familiar normal “iris” turn-on and abnormal “iris” turn-off behavior. The turn- on time is about 130 ps and the turn-off time is about 170 ps. In 1 ns and 2 ns gating modes, the fully-on time of optical gating almost is equal to the width of the electrical gating pulse, In 0.5 ns, 0.25 ns and 0.125 ns modes, the fully-on time is less than the width of the electrical gating pulse, especially in the 0.125 ns gating mode, and the image in fully-on phase is not observed. The width at 90% of the peak of the optical gating time response curve may better characterize the fully-on time of optical gating.

Dynamic switching operation of diamond MOSFETs with NO2 p-type doping and Al2O3 gate insulation and passivation

Diamond metal–oxide–semiconductor field-effect transistor (MOSFET) exhibited durable and stable dynamic switching characteristics at an unprecedentedly high voltage of −105 V. Switching turn-on and turn-off times were measured to be 7.64 and 4.93 ns, respectively, with a corresponding total switching loss of 20.03 pJ for a load resistance of 50 Ω. No Miller effect was observed due to the low Miller capacitance of 11 pF/mm. This study suggests the potentiality of diamond MOSFETs in prospective high-voltage, high-speed applications.

A fast-switching and ultra low-loss snapback-free reverse-conducting SOI-LIGBT with Adjustable Carrier Technology

A snapback-free Reverse-Conduction Silicon On Insulator Lateral Insulate Gate Bipolar Transistor (RC SOI-LIGBT) with Adjustable Carrier Technology (ACT LIGBT) is proposed in this paper. ACT LIGBT adds Semi-Insulating Polycrystalline Silicon (SIPOS) material on the extended gate dielectric, and introduces the potential of the surface SIPOS into the P-type drift region (P-Drift) through SiO2 trenches. ACT LIGBT generates the inversion layer of electrons in the P-Drift due to the linear potential distribution brought by the high resistance characteristic of SIPOS, resulting in the adjustment of the number of electrons and holes, and forming the technology of ACT. Additionally, ACT LIGBT adds a hole extraction path during it turned off. Meanwhile, compared to SSA LIGBT, ACT LIGBT optimized the BV (700V) by 34 %, while also optimizing the Von (1.69V) by 25 %, turn-off time (toff = 12ns) by 92 %, turn-off loss (Eoff = 0.69 mJ/cm2) by 79 %, and reverse recovery charge (Qrr = 32.98 μC/cm2) by 32.5 %, ultimately achieving a better compromise relationship among BV, Von, toff, Eoff, and Qrr.

Research on transformer based online condition monitoring method for IPM

Abstract The Intelligent Power Module (IPM) has the integrated packaging, leading to the advantages of convenient use, safety and reliability. However, once it fails, it will cause the whole power supply system to be inoperative, and it is necessary to perform online Condition Monitoring (CM) of the IPM. In this paper, we extract the aging characteristics such as dynamic equivalent resistance, peak-to-peak value, switching frequency, and turn-off time only from the voltage and current of IPM drain–source port, and then propose a non-intrusive online CM method for the IPM based on the transformer neural network (TNN). We analyse the internal aging mechanism of the IPM, the changing law of aging features, and construct multi-dimensional aging fusion features, and then the TNN model is used to monitor early parameters drift of multi-dimensional fusion feature vectors and realize the accurate online prediction of IPM health condition. The experimental analysis results show that the fault prediction accuracy reaches 96%, and can realize the health CM under the condition of noise interference, weak aging features and few external observable points.

A fast-switching low-loss field-stop IGBT with dual control gate of SIPOS material

A fast-switching low-loss field-stop insulated gate bipolar transistor with a dual control gate (DIGBT) of a semi-insulating polycrytalline silicon (SIPOS) material is proposed in this paper. Because the SIPOS has uniform high resistance, it has an approximate linear electric potential distribution. When DIGBT conducts, the higher electric potential on SIPOS causes the P-type drift region (P-drift) to generate an inversion layer of electrons, adjusting the number of carriers and making the generation of non-equilibrium carriers no longer dependent on the doping concentration in P-drift (Nd) but on the electric potential distribution on SIPOS. Therefore, it can solve the contradiction among the breakdown voltage, forward voltage drop [VCE(sat)], turn-off time (toff), and turn-off loss (Eoff) caused by the Nd. Through Technology Computer Aided Design (TCAD) simulation, the VCE(sat) of DIGBT is 30.6% lower than that of SJFS IGBT. Meanwhile, DIGBT reduces the toff by 62.8% while reducing the Eoff by 83.0% compared to SJFS IGBT. In addition, the static latch-up I–V and the forward biased safe operating area of the DIGBT have been significantly improved. This paper adjusts the number of carriers through the characteristics of SIPOS material, enabling the above-mentioned physical phenomena to be applied in insulated gate bipolar transistor power devices and achieving device performance breakthroughs.

A Novel High-Speed Split-Gate Trench Carrier-Stored Trench-Gate Bipolar Transistor with Enhanced Short-Circuit Roughness.

A novel high-speed and process-compatible carrier-stored trench-gate bipolar transistor (CSTBT) combined with split-gate technology is proposed in this paper. The device features a split polysilicon electrode in the trench, where the left portion is equipotential with the cathode. This design mitigates the impact of the anode on the trench gate, resulting in a reduction in the gate-collector capacitance (CGC) to improve the dynamic characteristics. On the left side of the device cell, the P-layer, the carrier-stored (CS) layer and the P-body are formed from the bottom up by ion implantation and annealing. The P-layer beneath the trench bottom can decrease the electric field at the bottom of the trench, thereby improving breakdown voltage (BV) performance. Simultaneously, the highly doped CS layer strengthens the hole-accumulation effect at the cathode. Moreover, the PNP doping layers on the left form a self-biased pMOS. In a short-circuit state, the self-biased pMOS turns on at a certain collector voltage, causing the potential of the CS-layer to be clamped by the hole channel. Consequently, the short-circuit current no longer increases with the collector voltage. The simulation results reveal significant improvements in comparison with the conventional CSTBT under the same on-state voltage (1.48 V for 100 A/cm2). Specifically, the turn-off time (toff) and turn-off loss (Eoff) are reduced by 38.4% and 41.8%, respectively. The short-circuit current is decreased by 50%, while the short-circuit time of the device is increased by 2.46 times.

Low-loss carrier stored trench-gate bipolar transistor with split-gate optimization

In the conventional carrier stored trench-gate bipolar transistor (CSTBT) device, a lower conduction voltage drop (Von) can be achieved with higher carrier stored (CS) layer dosage. However, the trench bottom is weakened leading to easier breakdown under high electrical field. In this work, the trench-gate structure of the conventional CSTBT is optimized and split into three components. The bottom and top left components of the split trench structure are equipotential with the emitter, which effectively eliminated the impact of collector on the trench gate with reduced gate charge (Qgc). In addition, another n-type CS layer is formed adjacent to the emitter to further enhance the hole carrier storage effect near emitter. This improves the trade-off between Von and turn-off time (Toff) without breakdown voltage (BV) degradation. The simulation results show that in comparison with the conventional CSTBT, the proposed device exhibits 64.6% reduction in Qgc under the same Von, while the turn-off time (Toff) and the saturation current are reduced by 14.9% and 43.4%, respectively. The short-circuit capability is also studied with 2.83 times improvement. Our proposed device shown here provides a feasible and attractive approach for advanced high-performance power electronics applications.

Superjunction IGBT with split carrier storage layer

Abstract The Insulated Gate Bipolar Transistor (IGBT) is crucial in high-voltage applications due to its characteristics like breakdown voltage (BV) and on-state voltage VCE(sat). However, its slower turn-off time, attributed to hole mobility, restricts its frequency range. Techniques such as the carrier storage layer (CSL) and super-junction (SJ) structures aim to optimize BV and VCE(sat) through hole density and field distribution. Combining CSL and SJ offers advantages, yet challenges remain regarding E-field concentration. 
In this work, the split CSL concept introduces a solution by optimizing BV and Eoff through effective field distribution and hole extraction acceleration respectively while maintaining VCE(sat). Split CSL, which is divided into a high doping layer and a low doping layer, reduces the burden on the gate oxide by distributing the E-field evenly when in the off-state due to the difference in doping concentration. And during turn-off, hole current is concentrated on LDL, which has relatively low resistance, thereby accelerating hole extraction. Simulation-based results showcase improvements in the proposed structure's properties. The further optimization of high doping layer (HDL) and low doping layer (LDL) concentrations enhances the structure's performance. It is clear that the split CSL structure presents potential for advancing IGBT capabilities. The application of the split CSL structure resulted in significant improvements: the turn-off time was reduced by 32.4% and the breakdown voltage increased by 32.5 V compared to conventional CSL-SJ structures. These enhancements highlight the effectiveness of the split CSL design in optimizing the IGBT’s performance attribute.

Accurate low-energy pulse system for intravascular lithotripsy

In response to biomedical imperatives, a novel approach is presented for the endovascular management of atherosclerosis. This approach is grounded in the electrohydraulic effect of a precisely controlled low-energy pulse discharge system, coupled with sequential control within the incomplete discharge electrode, to generate shockwaves aimed at softening blood vessels and rupturing calcified plaques. Theoretical analysis encompassed circuit design, control timing, and operational processes, while experimental investigations demonstrated precise control of non-oscillation and incomplete discharge by adjusting key parameters. Utilizing a 3 kV DC high-voltage power supply, a 220 nF capacitor, and two sets of 3.3 Ω resistors in parallel, with pin–plate electrodes as the load for discharge in normal saline, resulted in a 1 kV reduction in voltage across the capacitor and a peak current of 170 A. Energy release occurred through non-oscillatory and incomplete discharge, effectively generating shockwaves with peak pressures of 5–10 MPa at distances of 1–2 mm from the discharge center to treat calcified lesions. Compared with the existing intravascular lithotripsy devices, the shockwave system realizes accurate control of discharge energy by adjusting the turn-off time of incomplete discharge so as to realize accurate control of shockwave energy. Doctors can choose different intensities of shockwaves according to different degrees of calcification in the treatment process so as to minimize the discomfort caused by shockwaves and improve safety. Valuable insights are provided for intravascular lithotripsy devices in engineering.

Design and investigation of double-RESURF SOI-LIGBT with carrier-storage layer in P-top

A novel double-RESURF SOI-LIGBT with carrier-storage layer in P-top (CSLP-LIGBT) is proposed and studied by simulation. The carrier storage layer avoids direct connection between the P-top region and the P+ region, enhancing the carrier storage effect in the drift region during the on-state. CSLP-LIGBT provides a fast hole-extraction channel during the turn-off transient, shortening the turn-off time and decreasing the turn-off loss (Eoff). The simulation results show that at the same on-state voltage (VCE(sat)) of 1.12V and temperature is set to 300K, the turn-off loss of the CSLP-LIGBT is 25.49%, 35.59%, and 44.12% lower than that of the double-gate SOI-LIGBT (DG-LIGBT), double-RESURF SOI-LIGBT with floating P-top (FPDR-LIGBT), and double-RESURF SOI-LIGBT (DR-LIGBT), respectively. The CSLP-LIGBT effectively improves the tradeoff relationship between VCE(sat) and Eoff without sacrificing breakdown voltage and process complexity.

A 4H-SiC p-channel insulated gate bipolar transistor with higher breakdown voltage and superior V F·C res figure of merit

A silicon carbide p-channel insulated gate bipolar transistor (IGBT) with higher breakdown voltage (BV) and low V F·C res figure of merit (FOM) has been simulated, fabricated, and characterized successfully. The proposed IGBT adds two n-type implant regions in the junction FET (JFET) area and increases the gate oxide thickness above the JFET area to reduce the reverse transfer capacitance (C res) and gate oxide electric field (E ox). The proposed structure notably lowers E ox below 3 MV cm−1 while elevating the BV to 16.6 kV. A new FOM of V F·C res is defined to evaluate the trade-off between the on-state and the C res characteristics. The experimental results demonstrate that a lower V F·C res FOM of 0.369 V·pF is achieved from the proposed IGBT with a reduction of 66.4%, compared to the conventional current spreading layer IGBT. Meanwhile, the simulated turn-on and turn-off times of the proposed IGBT are reduced by 29.4% and 20%, respectively.

A closer look to the factors affecting the switching transient times of optocouplers

The significant parameters for a high-speed optoelectronic switch were the transient times. In the time domain, there is a time elapsed on the order of microseconds between applying a current pulse and seeing an output. Therefore, the present work aimed to give a closer look on the factors affecting the transient times of the optocoupler switching action, namely; delay (td)-, rise (tr)-, in addition to storage (ts)- and fall (tf)-times. The turn-on time (Ton = td + tr) and turn-off time (Toff = ts + tf) of the optocoupler (type 4N25) were investigated and plotted under the influence of different operating conditions such as: load resistance (RL), forward LED drive current (IF), bias collector voltage (VCC), emitter–base resistance (RBE), and ambient temperature.

A Novel Diagnosis Method for Interturn Short-Circuits in SRMs by Tracking Post Turn-Off Phase Currents Under Current Chopping Control

Current chopping control (CCC) is widely preferred for low and medium-speed applications in switched reluctance motor drives. With precise current regulation, the consequence of inter-turn short-circuits is not reflected much in the faulty phase current. Also, the fault features are difficult to extract in the online mode for minor short-circuits. Moreover, ITSCs are responsible for hot spots in the defective winding, ultimately leading to a complete winding short-circuit due to persisting heating effect. Even the associated complications of SRMs like torque ripple, noise and vibrations are amplified to a greater extent under ITSCs. Therefore, diagnosing ITSCs is critical to shun such unwanted characteristics and failures. This article proposes a simple and novel method to diagnose ITSCs even with minor short-circuits in SRMs operating under CCC. With the reduction in the inductance due to ITSCs, the decay time of the faulty phase current post turn-off also reduces. This variation is monitored for all the phase currents within their respective aligned rotor positions to diagnose ITSC. The proposed method has better detection reliability regarding diagnosis under varying load conditions. The scheme is validated experimentally on a test setup of a customized four-phase SRM having winding taps for emulating ITSCs.

Novel majority carrier accumulation insulated gate bipolar transistor with Schottky junction

Insulated gate bipolar transistor (IGBT) is the core of modern power semiconductor device, and has been widely used due to its excellent electrical characteristics. A novel majority carrier accumulation mode IGBT with Schottky junction contact gate semiconductor layer (AC-SCG IGBT) is proposed and investigated by TCAD simulation in this article. When the AC-SCG IGBT is in the on-state, a forward bias is applied to the gate. Due to the very low forward voltage drop (<i>V</i><sub>F</sub>) of the Schottky barrier diode, the potential of the gate semiconductor layer is almost equal to the gate potential, which can accumulate a large number of majority carrier electrons in the drift region. In addition to the electrons existing, these accumulated electrons increase the conductivity of the drift region, thus significantly reducing <i>V</i><sub>F</sub>. Therefore, the doping concentration of the drift region is not limited by <i>V</i><sub>F</sub>. The lightly doped drift region can make AC-SCG IGBT have a higher breakdown voltage (BV). Moreover, it also reduces the barrier capacitance in the turn-off process, thus the overall Miller capacitance is small, which can quickly turn off and reduce the turn-off time (<i>T</i><sub>off</sub>) and turn-off loss (<i>E</i><sub>off</sub>). The simulation results indicate that at the BV of 600 V, the <i>V</i><sub>F</sub> of 0.84 V for the proposed AC-SCG IGBT is reduced by 46.2% compared with that for the conventional IGBT (<i>V</i><sub>F</sub> of 1.56 V). The <i>E</i><sub>off</sub> of the AC-SCG IGBT (0.77 mJ/cm<sup>2</sup>) is reduced by 52.5% compared with that for the conventional IGBT (1.62 mJ/cm<sup>2</sup>), and the <i>T</i><sub>off</sub> (155.8–222.7 ns) is reduced by 30%. The contradiction between <i>V</i><sub>F</sub> and <i>E</i><sub>off</sub> is eliminated. In addition, the proposed AC-SCG IGBT has a better anti-latch-up capability and is coupled with its higher BV, so it has a larger forward biased safe operating area (FBSOA). The proposed novel structure meets the development requirements for future IGBT device performance, and has great significance for guiding the development of the power semiconductor device field.

Design and Performance Analysis of a [8/8/8] Charge Domain Mixed-Signal Multiply-Accumulator

This article describes the design and performance analysis of a charge domain mixed-signal multiply-accumulator (MAC) using RDAC, CDAC, and SAR-ADC with an 8-bit resolution for input, weight, and output. The arithmetic accuracy is mainly determined by the ADC, and the gain error has a significant impact. The mismatches and thermal noises of the RDAC and the CDAC are averaged by the number of multiply-accumulate units m connected to one ADC. As a result, if m is large enough, mismatches and thermal noises have a limited impact on the computation accuracy. Most of the computational energy is determined by the energy consumed by the SAR-ADC, and the computational energy per operation can be reduced by increasing m. This last metric is mainly determined by the charge and discharge energy of the CDAC for sufficiently large m values. Furthermore, since RDAC consumes energy unnecessarily, the turn-off timing of RDAC should be optimized. These MAC units have been designed and prototyped using 28 nm CMOS technology, integrating 12,288 arithmetic units while operating at 180 MHz, resulting in an arithmetic speed of 4.4 TOPS. The r-MVM accuracy is about 1% and a high energy efficiency of 240 TOPS/W as a MAC macro and 64.4 TOPS/W as a system has been achieved.

An 800V ultra-low loss field-stop insulated gate bipolar transistor with extended polysilicon gate structure

This paper proposed a Insulated Gate Bipolar Transistor with extended polysilicon gate structure (EPG IGBT) based on P-type drift region (P-Drift), which has electron inverse and accumulation layer. It designs the gate as an extended gate structure with a Bipolar Junction Transistor (BJT), extending into the collector region, and the BJT is always blocked during the switching process. When the EPG IGBT is conducting, the Nj region has a constant positive voltage, which causes the P-Drift to form an electron inversion layer and conduct. Through TCAD simulation, the EPG IGBT maintained the same Breakdown Voltage and turn-off time, while reducing its forward voltage drop (VCE(sat) = 0.98 V) and turn-off loss (Eoff = 0.89 mJ/cm2) by 36 % and 44 %, respectively, compared with FSSJ IGBT of the same process (VCE(sat) = 1.53 V, Eoff = 1.58 mJ/cm2). In addition, the static latch-up I–V and Forward Biased Safe Operating Area (FBSOA) of the EPG IGBT have been significantly improved, providing a new approach for optimizing IGBT.

Intelligent Personalized Lighting Control System for Residents

The demand for personalized lighting environments based on households is steadily increasing among users. This article proposes a novel intelligent control system for personalized lighting in home environments, aiming to automatically capture user information, such as homecoming time and light switching behavior, in order to train a model that intelligently regulates the lights for users. Facial recognition technology is employed by this system to identify users and record their lighting data. Subsequently, nine commonly used machine learning models were evaluated, revealing that the error back-propagation neural network algorithm exhibits excellent performance in time-series analysis. The BPNN weights were optimized using genetic algorithms, resulting in an improved coefficient of determination (R2) of 0.99 for turn-on time and 0.82 for turn-off time test sets. Furthermore, testing was conducted on data collection duration which demonstrated that even with only 20 time-series data collected from new users, the model still displayed exceptional performance in training prediction tasks. Overall, this system effectively identifies users and automatically adjusts the lighting environment according to their preferences, providing comfortable and convenient lighting conditions tailored to individual needs. Consequently, a broader goal of energy conservation and environmental sustainability can be achieved.

Stability Analysis for Hybrid Conduction Mode Single-Inductor Dual-Output DC–DC Converter With Dynamic-Freewheeling Control and Dynamic Ramp-Compensation

Hybrid conduction mode (HCM) is gradually applied in single-inductor dual-output (SIDO) dc-dc converter as its advantages of reducing switching loss and minimizing cross-regulation. However, it shows that the circuit parameters will affect the stability and restrict its operation range, which causes the converter to operate in non-HCM and these advantages are lost. In this paper, to figure out this phenomenon, eight different operation modes of the HCM SIDO buck converter are analyzed. On this basis, a three-dimensional discrete-time model, which is suitable for variable-frequency control, is established. And then, the effect of output capacitors and its equivalent series resistances (ESRs), load resistors, input voltage and output voltages, constant turn-off time on the stability is discussed. The study results show that the stability and operation mode is sensitive to the difference circuit parameters and control parameters. In addition, the dynamic ramp-compensation based on inductor current is proposed and analyzed for stabilization control, which can broaden the stable operation range of this converter. Finally, experimental results validate the accuracy of proposed theoretical analysis.

Research on Online Monitoring Method for Bond Wire Fatigue Applied to IGBT Module

Bond wire fatigue is a prominent problem affecting the reliability of IGBT modules and power electronic converters, and has thus received much attention in the research community. As bond wire fatigue leads to changes in the gate circuit parameters, it affects the IGBT turn-off process. Based on this finding, this paper proposes a fatigue evaluation method for bond wire based on IGBT turn-off time. This includes constructing a turn-off time-bond wire fatigue model that considers the impact of changes in collector current, and developing a control software that utilizes the coupling relationship between the Kelvin terminal voltage VeE and turn-off time for the online extraction of IGBT turn-off time. In summary, the proposed online monitoring method of IGBT bond wire fatigue based on turn-off time can help improve the reliability of power electronic converters.

Surface alignment of nematic liquid crystals by direct laser writing of photopolymer alignment layers

ABSTRACT We demonstrate the fabrication of good quality surface alignment layers on glass by Direct Laser Writing method using a 2-photon polymerisation technique. We use commercially available photosensitive resins to print alignment layers by scanning the focal point of a femtosecond laser near the resin-glass interface. This results in down to ~ 100 nm thin alignment layers that provide good planar anchoring of 5CB and MLC13300, with the easy axis of alignment along the scanning direction. The azimuthal anchoring strength is ~ 5 × 10−6 J/m2 and is an order of magnitude weaker compared to commercial rubbed polyimide alignment layer. The threshold voltage for Fréedericksz transition in a 90° twisted nematic cell is slightly increased compared to conventional rubbed polyimide for printed alignment layers. The turn-on switching time is longer for printed layers compared to polyimide alignment layers, whereas the turn-off time is shorter for printed alignment layers. The advantage of this new method is in its flexibility, as we demonstrate printing of complex surface alignment patterns with alignment layer thickness below 100 nm.