Turn-off Delay Time Research Articles

Real-Time Degradation Level Assessment of IGBT Gate Oxide Layer Using Turn-Off Delay Time

Real-Time Degradation Level Assessment of IGBT Gate Oxide Layer Using Turn-Off Delay Time

A Junction Temperature Online Monitoring Method for IGBTs Based on Turn-off Delay Time

A Junction Temperature Online Monitoring Method for IGBTs Based on Turn-off Delay Time

Investigation and Comparison of Temperature-Sensitive Electrical Parameters of SiC mosfet at Extremely High Temperatures

Due to the excellent silicon carbide (SiC) material characteristics, SiC MOSFETs can operate at extremely high temperatures and can be used in harsh environment applications. In this case, it is crucial to ensure the reliability of the power electronic systems. The temperature-sensitive electrical parameters (TSEPs) have been used for online junction temperature monitoring to monitor the health condition of the SiC MOSFET at low temperatures (<175℃). However, the performance of the TSEPs at extremely high temperatures is still unknown, and the influence of temperature on the TSEPs of SiC MOSFET at extremely high temperatures is unclear. In this article, the theoretical mechanisms of the impact of the extremely high temperature on TSEPs are investigated in detail. In particular, the different effects of high temperature on the turn-on delay time and turn-off delay time are discussed carefully. Based on the high-temperature characteristic test method proposed, the TSEPs of SiC MOSFET (including static and dynamic characteristics) are tested and analyzed comprehensively from room temperature to 375℃. And the sensitivity and linearity of the TSEPs in different temperature ranges are analyzed and compared. According to the results, threshold voltage and turn-off delay time are the two TSEPs with good sensitivity and linearity over a wide temperature range (from room temperature to 375℃). And the linearity of turn-off delay time is the best among all TSEPs over a wide temperature range.

A Novel Three-Step Commutation Method for Direct Matrix Converter Free From Inrush Current and Voltage Error

The direct matrix converter is a well-accepted topology for AC/AC converters. The commutation method should be considered in the direct matrix converter topology to avoid failures caused by the input short circuit and output open circuit during commutations. The conventional three-step commutation method of input voltage not only avoids the aforementioned failures but also removes errors between actual and command output voltage. However, it increases the number of hard switching and the flow of inrush current originating from the mismatch between the turn-on and turn-off delay time of switches. This paper proposes a new three-step commutation method that eliminates inrush current and reduces the number of hard switching. In this way, the conversion efficiency is improved, and circuit hazards caused by inrush current are over. Meanwhile, the proposed commutation method keeps the advantage of canceling the voltage error of conventional three-step commutation. Noteworthy that the proposed commutation method is introduced based on a novel fixed-slope direct duty ratio PWM simplifying the practical implementation. The performance and effectiveness of the proposed method have been verified by simulation and experimental results.

An Online Junction Temperature Monitoring Correction Method for SiC MOSFETs at Different Parasitic Parameters

Due to the remarkable performance of silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) on high temperature, it is promising in future applications in various applications. The accurate online junction temperature based on dynamic temperature-sensitive electrical parameters (TSEPs) is significant for the protection and condition monitoring, which can prolong or monitor the lifetime of SiC MOSFET devices. In this article, four different dynamic TSEPs, including turn-on delay time, turn-off delay time, and maximum current turn-on and turn-off switching rates, are theoretically analyzed taking the parasitic parameters into consideration. The experimental analysis of the influence of parasitic parameters ’ dynamic TSEPs is carried on using a buck converter test setup. Based on the theoretical and experimental analyses, a junction temperature correction method is proposed for SiC MOSFET. The online junction temperature monitoring experiments are used to verify the accuracy and effectiveness of the proposed method. The results show that the proposed correction method can largely eliminate the junction temperature monitoring error at different parasitic parameters. The maximum measurement error is reduced from 147 °C to 4.7 °C after correction.

An optimized parameter design method of SiC/Si hybrid switch considering turn-off current spike

In order to reduce the switching loss of SiC MOSFET/Si IGBT (SiC/Si) hybrid switch, the switching mode that turn off the Si IGBT prior to the SiC MOSFET is generally adopted to achieved the zero-voltage switching operation of IGBT. The minority carrier in N-base region of the IGBT are recombined in the form of exponential attenuation due to the conductivity modulation effect. When the SiC MOSFET is turned off, if the carrier recombination process of the IGBT is not finished, it needs to bear a large collector–emitter voltage change rate, resulting in apparent current spike. This current spike will increase the current stress of the device and produce additional turn-off loss. The equivalent model of double pulse test circuit of SiC/Si hybrid switch considering parasitic parameters is established, and the turn-off transient process is given analytically. The influence of turn-off delay time, circuit parameters and working conditions on current spike are analysed quantitatively. Combined with the consideration of device stress and comprehensive turn-off loss, an optimized circuit design method of SiC/Si hybrid switch considering turn-off current peak is proposed, which provides theoretical and design guidance for high reliability and high efficiency SiC/Si-based converters.

Dynamic Gate Delay Time Control of Si/SiC Hybrid Switch for Loss Minimization in Voltage Source Inverter

The voltage source inverter (VSI) based on the Si/SiC hybrid switch (HyS) offers a better cost/performance tradeoff than the full-SiC VSI design. However, the Si/SiC hybrid VSI bears huge power losses with fixed gate turn-off delay time. In this article, a novel dynamic optimal gate turn-off delay time control method of Si/SiC HyS-based VSI is proposed to achieve the maximum efficiency over a wide load range. The optimal gate turn-off delay time is obtained by a load current-based mathematic power loss model. A 20-kHz 5-kW prototype of the single-phase constant current (CC) VSI using a 1200-V/25-A insulated gate bipolar transistor (IGBT) and a 1200-V/12.5-A SiC MOSFET is built to validate the proposed method. In comparison with the fixed gate turn-off delay time control method, the proposed method achieves 8% total power loss reduction and 0.24% conversion efficiency improvement at 1.5-kW output power.

A Fault Detection Method for Partial Chip Failure in Multichip IGBT Modules Based on Turn-Off Delay Time

Multichip IGBT module has been widely used in high-power converters. Detecting the status of the IGBT chip is a cost-effective approach to improving the reliability of power devices. This article proposes a novel method based on turn-off delay time to detect chip fault in multichip IGBT modules. First, the effect of chip failure on the turn-off process is analyzed, which causes a decrease in turn-off delay time. Then, a detection method of chip failure based on turn-off delay is proposed, which is validated by experimental results. Furthermore, the effects of chip failure on turn-off delay time in different working conditions are investigated through effective experimental results. The tested results show that the proposed method not only has high linearity and sensitivity to chip failure, but can also eliminate the influence of working environments on detection. The proposed method can be used to monitor the health status of multichip modules and is of great significance for enhancing operation reliability.

Monitoring Initial Solder Layer Degradation in a Multichip IGBT Module via Combined TSEPs

With the development of high power converters, the safe operation of large IGBT modules with parallel chips is of increasing importance. In a multichip module, uneven solder layer degradation translates into higher thermal resistance for some of the chips, leading to junction temperature differences between them. However, the specific meaning of a virtual junction temperature extracted from any external electric characteristic parameter of the module is not yet clear. This paper studies the physical meanings of the temperatures estimated by the threshold voltage and the Miller platform duration as well as the quasi turn- off delay time. Experimental results show that the temperature estimated from the threshold voltage is close to the highest temperature of all the chips, while that estimated from the Miller platform duration or quasi turn-off delay time is close to the average chip temperature. Making use of the difference between the two, this paper proposes a new method to monitor the initial solder layer degradation in the multichip IGBT module. Such a method using combined temperature sensitive electric parameters (TSEPs) is verified for different levels of degradation.

Ruggedness of Dual-GCT against dynamic avalanche and surge current

Based on multi-cell structure model, the ruggedness of Dual Gate Commutated Thyristor (Dual GCT) against dynamic avalanche and surge current is examined by the device simulation. The simulation results of turn-off behavior show at smaller turn-off delay time, the current filament caused by dynamic avalanche arises in the GCT-A part, which is adverse for the device, and at larger turn-off delay time, the filament arises in the GCT-B part. And the carrier lifetime in the GCT-B part can also influence where the filament appears. Increasing the carrier lifetime of GCT-B part could improve the surge ruggedness of the device, but a compromise must be made between the turn-off and the surge ruggedness. Choosing the lifetime control process that can maximize the temperature dependency coefficient of the lifetime is proved to be an effective method to improve the surge ruggedness while ensuring the turn-off behavior well. Finally, a new Dual GCT structure with proper layout of anode short regions in the GCT-B part is proposed and it is validated by simulation to have excellent surge ruggedness.

Switching Time Delay Optimization for “SiC+Si” Hybrid Device in a Phase-Leg Configuration

Compared to SiC MOSFET, the switching loss of Si IGBT is much higher due to its slow switching speed and tail current. Si IGBT/SiC MOSFET hybrid switch device can reach to optimal performance with low static and dynamic loss, which can improve the current capacity of SiC devices and reduce the power loss of Si IGBT based converters. With the separated gate control signals, the switching moments of the two devices can be controlled independently to ensure Si IGBT under zero-voltage switching (ZVS) conditions. This measurement tends to reduce the switching loss of Si IGBT. However, the switching time delay between these two devices has significant impacts on its power loss. In this paper, the switching time delay optimization method is proposed to minimize the power loss of the hybrid switch. The static and dynamic characteristics of Si IGBT/SiC MOSFET hybrid-paralleled switch are studied, and a generalized power loss model for hybrid switch is developed. The influence of switching time delay on the characteristics of hybrid switch is analyzed and verified through double pulse tests in a phase-leg configuration. The experimental results show that the optimal turn-on delay time is that the two devices turn on at the same time and the turn-on loss can be reduced by about 73% compared with the solely Si IGBT and by about 52% compared with the solely SiC MOSFET. While the optimal turn-off sequence is that the Si IGBT turns off ahead of the SiC MOSFET. Under the proposed optimal turn-off delay time of the hybrid switch, the turn-off loss is reduced by about 61.4%. This optimization strategy is used in a Buck converter to verify the superiority of the SiC/Si hybrid switch and the optimal switching sequence. Simulation results show that the optimal switching sequence is consistent with theoretical analysis, and the efficiency is improved by 2.5% compared with Buck converter using solely Si IGBT.

Real-Time Device-Level Simulation of MMC-Based MVDC Traction Power System on MPSoC

Real-time simulation of device-level power electronic converter models plays an essential role in traction power systems by allowing accurate prediction of device stresses to design improved control and protection schemes. This paper proposes the electrothermal behavioral power electronic models for the modular multilevel converter (MMC)-based medium voltage direct current (MVDC) traction power system based on the Wiener–Hammerstein configuration. The new configuration introduces the carrier charge prerequisite dynamic transients before device turn-ON or turn-OFF operation. The equivalent carrier charge circuit is also proposed, and the first-order delay assumption of turn-ON and turn-OFF delay time has been proven by the device datasheet. The power electronic device models are implemented in a Xilinx® Zynq® multiprocessing system-on-chip platform. By utilizing hardware and software codesign, both 25- $\mu \text{s}$ time-step system-level and 100-ns time-step device-level transients can be captured in real time within a single device. The three-phase unbalance issue has been resolved by introducing the three-phase to single-phase MMC topology. In the case study, the MMC-based MVDC traction power system has been utilized for the performance of the proposed electrothermal behavioral power electronic models by the off-line simulation models on SaberRD® for device-level transients and PSCAD/EMTDC® for system-level transients.

Influence of base carrier lifetime on the characteristics of 4H-SiC BJTs

The optimum range of the base electron lifetime (τnB0) in silicon carbide (SiC) bipolar junction transistors (BJTs) is qualitatively investigated in this paper, considering both the static and dynamic performance. The TCAD simulation results show that there is tradeoff between the current gain (β) and the turn-off time (tF). With τnB0 increasing, both β and tF increase. However, with a fixed base width, the base transport factor tends toward saturation when τnB0 exceeds certain value. Thus, the eclectic values of base electron lifetime with different base thickness are obtained. The influence of the base drive current is also discussed. According to the charge control theory, the excessive storage charge caused by overdrive has a great influence on turn-off delay time (tD). To solve this, a suitable base drive current is necessary. For the common 4H-SiC BJT structure, appropriate base drive under variable base and collector doping concentration is suggested.

Improvement of Switching Speed of a 600-V Nonpunch-Through Insulated Gate Bipolar Transistor Using Fast Neutron Irradiation

Abstract Fast neutron irradiation was used to improve the switching speed of a 600-V nonpunch-through insulated gate bipolar transistor. Fast neutron irradiation was carried out at 30-MeV energy in doses of 1 × 10 8 n/cm 2 , 1 × 10 9 n/cm 2 , 1 × 10 10 n/cm 2 , and 1 × 10 11 n/cm 2 . Electrical characteristics such as current–voltage, forward on-state voltage drop, and switching speed of the device were analyzed and compared with those prior to irradiation. The on-state voltage drop of the initial devices prior to irradiation was 2.08 V, which increased to 2.10 V, 2.20 V, 2.3 V, and 2.4 V, respectively, depending on the irradiation dose. This effect arises because of the lattice defects generated by the fast neutrons. In particular, the turnoff delay time was reduced to 92 nanoseconds, 45% of that prior to irradiation, which means there is a substantial improvement in the switching speed of the device.

Elimination of collector current impact in TSEP-based junction temperature extraction method for high-power IGBT modules

Insulated gate bipolar transistor (IGBT) modules are widely employed in high-power conversion systems. Their junction temperature ranks as one of the most important factors in the reliability of power semiconductor devices. Thermo-sensitive electrical parameter (TSEP) is regarded as the promising solution to extract the junction temperature due to its non-invasion measurement, fast response and high accuracy. However, accurate collector current measurement is required if only the individual TSEP is adopted, which increases the complexity and cost. In this paper, the combined TSEP method is proposed to eliminate the influence of collector current (I C ), where the turn-off delay time (t doff ) and maximum decrease rate of I C (max dI C /dt) are adopted and combined. The two TSEPs both have linear relationships with junction temperature and I C . When they are combined mathematically, the influence of I C is eliminated. Experiments have been implemented to validate the effectiveness of the proposed approach. The comparison between combined TSEP and two individual TSEP methods are illustrated and analyzed.

Transmission line model for strained quantum well lasers including carrier transport and carrier heating effects.

This paper reports a new model for strained quantum well lasers, which are based on the quantum well transmission line modeling method where effects of both carrier transport and carrier heating have been included. We have applied this new model and studied the effect of carrier transport on the output waveform of a strained quantum well laser both in time and frequency domains. It has been found that the carrier transport increases the turn-on, turn-off delay times and damping of the quantum well laser transient response. Also, analysis in the frequency domain indicates that the carrier transport causes the output spectrum of the quantum well laser in steady state to exhibit a redshift which has a narrower bandwidth and lower magnitude. The simulation results of turning-on transients obtained by the proposed model are compared with those obtained by the rate equation laser model. The new model has also been used to study the effects of pump current spikes on the laser output waveforms properties, and it was found that the presence of current spikes causes (i) wavelength blueshift, (ii) larger bandwidth, and (iii) reduces the magnitude and decreases the side-lobe suppression ratio of the laser output spectrum. Analysis in both frequency and time domains confirms that the new proposed model can accurately predict the temporal and spectral behaviors of strained quantum well lasers.

Junction Temperature Extraction Approach with Turn-off Delay Time for High-voltage High-Power IGBT Modules

Thermo-sensitive electrical parameter (TSEP) approaches are widely employed in the junction temperature extraction and prediction of power semiconductor devices. In this paper, the turn-off delay time is explored as an indicator of a TSEP to extract the junction temperature from high-power insulated gate bipolar transistor (IGBT) modules. The parasitic inductor L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eE</sub> between the Kelvin and power emitter terminals of an IGBT module is utilized to extract the turn-off delay time. Furthermore, the monotonic dependence between the junction temperature and turn-off delay time is investigated. The beginning and end point of the turn-off delay time can be determined by monitoring the induced voltage v <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eE</sub> across the inductor L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eE</sub> . A dynamic switching characteristic test platform for high-power IGBT modules is used to experimentally verify the theoretical analysis. The experimental results show that the dependency between IGBT junction temperature and turn-off delay time is near linear. It is established that the turn-off delay time is a viable TSEP with good linearity, fixed sensitivity, and offers nondestruction on-line IGBT junction temperature extraction.

A dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor on a silicon-on-insulator substrate

In this paper, a novel dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor (DGDI LTIGBT) structure, which features a double extended trench gate and a dielectric inserted in the drift region, is proposed and discussed. The device can not only decrease the specific on-resistance Ron,sp, but also simultaneously improve the temperature performance. Simulation results show that the proposed LTIGBT achieves an ultra-low on-state voltage drop of 1.31 V at 700 A·cm−2 with a small half-cell pitch of 10.5 μm, a specific on-resistance Ron,sp of 187 mΩ·mm2, and a high breakdown voltage of 250 V. The on-state voltage drop of the DGDI LTIGBT is 18% less than that of the DI LTIGBT and 30.3% less than that of the conventional LTIGBT. The proposed LTIGBT exhibits a good positive temperature coefficient for safety paralleling to handling larger currents and enhances the short-circuit capability while maintaining a low self-heating effect. Furthermore, it also shows a better tradeoff between the specific on-resistance and the turnoff loss, although it has a longer turnoff delay time.

Analysis of Commercial Punch-Through IGBTs Behavior Under $^{60}$Co Irradiation: Turn-Off Switching Performances Evolution

This paper deals with the effects of <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sup> Co gamma irradiation on punch-through commercial insulated gate bipolar transistors turn-off switching behavior. The response of the threshold voltage, the gate-emitter leakage current, the collector leakage current, the collector-emitter breakdown voltage and the turn-off switching parameters under three different in situ gate biases are described. Charge trapping in the gate oxide causes the decrease of the threshold voltage. It is shown that the decrease of this parameter and the modifications in the Miller plateau level and width result in an increase of the turn-off delay time, the collector current fall-time, the collector-emitter voltage rise-time, and consequently an increase of the turn-off switching losses and a decrease of the turn-off overshoot collector-emitter voltage.

Fast turn-off of high voltage 4H–SiC npn BJTs from the saturation on-state regime

Fast turn-off of high-voltage (breakdown voltage ⩾ 3 kV) 4H–SiC npn bipolar junction transistors driven in a deeply saturated regime has been reported. In the conventional turn-off mode (base current break), the turn-off delay and current fall times are 80 ns and 100 ns, respectively. It is shown that these times can be made as short as 20 and 4 ns, respectively, if a reverse base current pulse of appropriate amplitude is applied to sweep out minority carriers from the base. The experimental values of delay and turn-off times well coincide with those calculated in terms of the charge control model.