Turbo Decoder Research Articles

A Simple Scheme for Realizing the Promised Gains of Downlink Nonorthogonal Multiple Access

In this paper, the downlink nonorthogonal multiple access (NOMA) system is studied where purely discrete input distributions are found that achieve the capacity region to within a constant gap without successive interference cancellation (SIC). The approach is a two-step approach where the corresponding linear deterministic model is first studied and the results are then systematically translated into purely discrete input distributions for the original model. A simple yet powerful coding scheme, which adopts off-the-shelf turbo codes with pulse amplitude modulations (PAM) is then used to simulate the proposed input distributions. Simulation results show that the proposed simple scheme under turbo decoding, both with and without SIC, can operate close to information-theoretic bounds of the proposed input distributions, which lies outside the achievable rate region of any orthogonal multiple access (OMA)-type scheme.

Performance Study of a Near Maximum Likelihood Code-Aided Timing Recovery Technique

In this paper, we propose a new code-aided (CA) timing recovery algorithm for various linear constant modulus constellations based on the Maximum Likelihood (ML) estimator. The first contribution is the derivation of a soft estimator expression of the transmitted symbol instead of its true or hard estimated value which is fed into the timing error detector (TED) equation. The proposed expression includes the Log-Likelihood Ratios (LLRs) obtained from a turbo decoder. Our results show that the proposed CA approach achieves almost as good results as the data-aided (DA) approach over a large interval of SNR values while achieving a higher spectral efficiency. We also derive the corresponding CA Cramer Rao Bounds (CRB) for various modulation orders. Contrarily to former work, we develop here the CRB analytical expression for different $M$ -PSK modulation orders and validate them through comparison to empirical CRB obtained by Monte Carlo iterations. The proposed CA estimator realizes an important gain over the nondata-aided approach (NDA) and achieves a smaller gap when compared to its relative CA CRB, especially at moderate SNR values where modern systems are constrained to work.

Design of QPP Interleavers for the Parallel Turbo Decoding Architecture

Parallel interleaver is an indispensable component for the parallel turbo decoder. The ever increasing data rates motivated by throughput-intensive applications result in higher parallelism of turbo decoder design, rendering the efficient realization of the interleaver a highly challenging work. This paper addresses the design of quadratic permutation polynomial (QPP) interleaver for the symbol-based serial MAP (SMAP) and the cross MAP (XMAP) parallel decoding. To circumvent the access conflicts incurred by the randomness of the interleaving function, the stratssonably position soft outputs of maximum a-posteriori (MAP) decoders in memory instances is firstly investigated. On this basis, a hardware-friendly parallel interleaver architecture is proposed by utilizing the algebraic properties of QPP function. Theoretical evaluation and experimental results demonstrate that the proposed design gains boosted hardware efficiency compared to existing schemes, and is applicable to both SMAP and XMAP decoding with arbitrary parallelism.

Turbo Quantization of Oversampled Signals

We present a new iterative quantization procedure for oversampled frames with guaranteed convergence and stability. The procedure uses similar concepts to that of turbo decoding in the context of error control coding. The quantization process is modeled as a quadratic integer-programming problem. A trellis structure is introduced to solve the problem, where the quantized coefficients represent a path through the trellis diagram. The quantization metric is iteratively improved through turbo iterations by exchanging quantization extrinsic information. The proposed procedure is shown to provide significant improvement over prior art in quantization and integer programming.

Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression

This brief proposes a new compression technique of next-iteration initialization metrics for relaxing the storage demands of turbo decoders. The proposed scheme stores only the range of state metrics as well as two indexes of the maximum and minimum values, while the previous compression methods have to store all of the state metrics for initializing the following iteration. We also present a hardware-friendly recovery strategy, which can be implemented by simple multiplexing networks. Compared to the previous work, as a result, the proposed compression method reduces the required storage bits by 30% while providing the acceptable error-correcting performance in practice.

Robust Turbo Analog Error Correcting Codes Based on Analog CRC Verification

In this paper, a new analog error correcting code with an iterative decoder is presented for real-valued signals corrupted by impulsive noises. In the proposed algorithm, a redundancy coding matrix is implemented as an analog version of the cyclic redundancy check (CRC) that is commonly used for data verification in digital communication. On the basis of this analog CRC, we propose an alternate decoding scheme with iterative decoding. In each iteration of the algorithm, the problem of decoding the long block code is decoupled into a set of parallel LP/LASSO subproblems. In the sparse noise model, this leads to a significant reduction in decoding complexity as compared to one-step convex programming decoding. The new code has improved correction capability compared to Zanko et al. In the almost sparse noise model, energy detectors are used to verify the decoding correctness of the inner code before transferring the result to the next iteration. In this case, the Turbo decoder shows little loss compared to the oracle bound based on least squares when the impulsive noises are perfectly known at the receiver.

Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit

Turbo codes comprising a parallel concatenation of upper and lower convolutional codes are widely employed in the state-of-the-art wireless communication standards, since they facilitate transmission throughputs that closely approach the channel capacity. However, this necessitates high processing throughputs in order for the turbo code to support real-time communications. In the state-of-the-art turbo code implementations, the processing throughput is typically limited by the data dependences that occur within the forward and backward recursions of the Log-BCJR algorithm, which is employed during turbo decoding. In contrast to the highly serial Log-BCJR turbo decoder, we have recently proposed a novel fully parallel turbo decoder (FPTD) algorithm, which can eliminate the data dependences and perform fully parallel processing. In this paper, we propose an optimized FPTD algorithm, which reformulates the operation of the FPTD algorithm so that the upper and lower decoders have identical operation, in order to support single instruction multiple data operation. This allows us to develop a novel general purpose graphics processing unit (GPGPU) implementation of the FPTD, which has application in software-defined radios and virtualized cloud-radio access networks. As a benefit of its higher degree of parallelism, we show that our FPTD improves the higher processing throughput of the Log-BCJR turbo decoder by between 2.3 and 9.2 times, when employing a high-specification GPGPU. However, this is achieved at the cost of a moderate increase of the overall complexity by between 1.7 and 3.3 times.

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

In wireless communication schemes, turbo codes facilitate near-capacity transmission throughputs by achieving reliable forward error correction. However, owing to the serial data dependencies imposed by the underlying logarithmic Bahl–Cocke-Jelinek–Raviv (Log-BCJR) algorithm, the limited processing throughputs of conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time wireless communication schemes. Motivated by this, we recently proposed a fully parallel turbo decoder (FPTD) algorithm, which eliminates these serial data dependencies, allowing parallel processing and hence offering a significantly higher processing throughput. In this paper, we propose a novel resource-efficient version of the FPTD algorithm, which reduces its computational resource requirement by 50%, which enhancing its suitability for field-programmable gate array (FPGA) implementations. We propose a model FPGA implementation. When using a Stratix IV FPGA, the proposed FPTD FPGA implementation achieves an average throughput of 1.53 Gb/s and an average latency of 0.56 $\mu \text{s}$ , when decoding frames comprising ${N}=720$ b. These are, respectively, 13.2 times and 11.1 times superior to those of the state-of-the-art FPGA implementation of the Log-BCJR long-term evolution (LTE) turbo decoder, when decoding frames of the same frame length at the same error correction capability. Furthermore, our proposed FPTD FPGA implementation achieves a normalized resource usage of 0.42 (kALUTs/Mb/s), which is 5.2 times superior to that of the benchmarker decoder. Furthermore, when decoding the shortest $N=40$ -b LTE frames, the proposed FPTD FPGA implementation achieves an average throughput of 442 Mb/s and an average latency of 0.18 $\mu \text{s}$ , which are, respectively, 21.1 times and 10.6 times superior to those of the benchmarker decoder. In this case, the normalized resource usage of 0.08 (kALUTs/Mb/s) is 146.4 times superior to that of the benchmarker decoder.

A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding

The multiplication of wireless communication standards is introducing the need of flexible and reconfigurable multistandard baseband receivers. In this context, multiprocessor turbo decoders have been recently developed in order to support the increasing flexibility and throughput requirements of emerging applications. However, these solutions do not sufficiently address reconfiguration performance issues, which can be a limiting factor in the future. This brief presents the design of a reconfigurable multiprocessor architecture for turbo decoding achieving very fast reconfiguration without compromising the decoding performances.

Stochastic Computing Improves the Timing-Error Tolerance and Latency of Turbo Decoders: Design Guidelines and Tradeoffs

Stochastic computing has been recently proposed for the hardware implementation of both low-density parity-check (LDPC) decoders and turbo decoders, which facilitate near-optimal error correction capabilities in wireless communication applications. Previous contributions have demonstrated that stochastic LDPC decoders offer an attractive tradeoff between their error correction capabilities, hardware performance, and timing-error tolerance. Motivated by this, we propose a pair of stochastic turbo decoder (STD) designs having significantly enhanced timing-error tolerance and significantly reduced processing latency. Moreover, we characterize the tradeoffs between chip area, energy efficiency, latency, throughput, and error correction capabilities of both the timing-error-tolerant STD and of the reduced-latency STD. We demonstrate that our proposed timing-error-tolerant STD operated at 1.20 V, with a clock period of 2.2 ns and in the presence of a three-standard deviation power supply variation of 7%, exhibits an unimpaired performance, compared with the state-of-the-art STD, operated at 1.20 V and 4 ns and with no power supply variations. This corresponds processing throughput improvement by a factor of 2.42 and energy consumption reduction by a factor of 4. Finally, we demonstrate that our proposed reduced-latency STD has a processing latency that is an order of magnitude lower than that of the state-of-the-art STD. This is despite reducing the chip area by a factor of 4, increasing the processing throughput by a factor of 65, while consuming only 0.005 times the energy of the state-of-the-art STD, when using binary phase-shift keying for communication over an additive white Gaussian noise channel having ${E_{b}/N_{0}=3}$ dB.

VLSI Implementation of Fully Parallel LTE Turbo Decoders

Turbo codes facilitate near-capacity transmission throughputs by achieving a reliable iterative forward error correction. However, owing to the serial data dependence imposed by the logarithmic Bahl–Cocke–Jelinek–Raviv algorithm, the limited processing throughputs of the conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time communication schemes. Motivated by this, we recently proposed a floating-point fully parallel turbo decoder (FPTD) algorithm, which eliminates the serial data dependence, allowing parallel processing and hence significantly reducing the number of clock cycles required. In this paper, we conceive a technique for reducing the critical datapath of the FPTD, and we propose a novel fixed-point version as well as its very large scale integration (VLSI) implementation. We also propose a novel technique, which allows the FPTD to also decode shorter frames employing compatible interleaver patterns. We strike beneficial tradeoffs amongst the latency, core area, and energy consumption by investigating the minimum bit widths and techniques for message log-likelihood ratio scaling and state metric normalization. Accordingly, the design flow and design tradeoffs considered in this paper are also applicable to other fixed-point implementations of error correction decoders. We demonstrate that upon using Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm low-power technology for decoding the longest long-term evolution frames (6144 b) received over an additive white Gaussian noise channel having $E_{b}/N_{0}=1~ \text {dB}$ , the proposed fixed-point FPTD VLSI achieves a processing throughput of 21.9 Gb/s and a processing latency of $0.28~ \mu \text {s}$ . These results are 17.1 times superior to those of the state-of-the-art benchmarker. Furthermore, the proposed fixed-point FPTD VLSI achieves an energy consumption of $2.69~ \mu \text {J}$ /frame and a normalized core area of $5~ \text {mm}^{\vphantom {R^{'}}2}/\text {Gb/s}$ , which are 34% and 23% lower than those of the benchmarker, respectively.

Correction Impulse Method for Turbo Decoding over Middleton Class-A Impulsive Noise

The correction impulse method (CIM) is very effective to achieve low error rates in turbo decoding. It was applied for transmission over Additive White Gaussian Noise (AWGN) channels, ...

Joint Turbo Decoding for Overloaded MIMO-OFDM Systems

To achieve an excellent error-correcting capability, the Third-Generation Partnership Project (3GPP) Long-Term Evolution (LTE) employs turbo codes as its forward error correction (FEC) standard. In addition, to achieve higher throughput, the LTE also implements multiple-input–multiple-output (MIMO) systems. Although a conventional turbo decoding scheme gives satisfactory performance in ideal MIMO systems, significant performance degradation occurs in an overloaded MIMO system when the number of transmit antennas is larger than that of receive antennas. In this paper, a joint decoding scheme for turbo codes, i.e., so-called joint turbo decoding, is proposed. In joint turbo decoding, calculations of soft information are conducted for each combination of bits from all streams instead of separately between each stream. In addition, to combine the trellis diagrams from all the streams, a super-trellis diagram is employed. The numerical results obtained through computer simulation show that the proposed scheme performs better than the conventional scheme, particularly in the case of an overloaded MIMO system. In the MIMO system with four transmit and two receive antennas, up to 2-dB performance enhancement can be attained at a bit error rate (BER) of 10−5. The proposed scheme also obtains improved throughput with a throughput/(SNR/stream) ratio close to the theoretical capacity of overloaded MIMO systems.

Performance and Complexity Evaluation of Iterative Receiver for Coded MIMO-OFDM Systems

Multiple-input multiple-output (MIMO) technology in combination with channel coding technique is a promising solution for reliable high data rate transmission in future wireless communication systems. However, these technologies pose significant challenges for the design of an iterative receiver. In this paper, an efficient receiver combining soft-input soft-output (SISO) detection based on low-complexity K-Best (LC-K-Best) decoder with various forward error correction codes, namely, LTE turbo decoder and LDPC decoder, is investigated. We first investigate the convergence behaviors of the iterative MIMO receivers to determine the required inner and outer iterations. Consequently, the performance of LC-K-Best based receiver is evaluated in various LTE channel environments and compared with other MIMO detection schemes. Moreover, the computational complexity of the iterative receiver with different channel coding techniques is evaluated and compared with different modulation orders and coding rates. Simulation results show that LC-K-Best based receiver achieves satisfactory performance-complexity trade-offs.

A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation

Matlab codes relating to the article Al-Dujaily, Ra'ed, Li, An, Maunder, Robert G, Mak, Terrence, Al-Hashimi, Bashir M. and Hanzo, Lajos (2016) A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation. IEEE Access.

Fully-Parallel Quantum Turbo Decoder

Quantum turbo codes (QTCs) are known to operate close to the achievable Hashing bound. However, the sequential nature of the conventional quantum turbo decoding algorithm imposes a high decoding latency, which increases linearly with the frame length. This posses a potential threat to quantum systems having short coherence times. In this context, we conceive a fully-parallel quantum turbo decoder (FPQTD), which eliminates the inherent time dependences of the conventional decoder by executing all the associated processes concurrently. Due to its parallel nature, the proposed FPQTD reduces the decoding times by several orders of magnitude, while maintaining the same performance. We have also demonstrated the significance of employing an odd–even interleaver design in conjunction with the proposed FPQTD. More specifically, it is shown that an odd–even interleaver reduces the computational complexity by 50%, without compromising the achievable performance.

On the LLR Metrics for DPSK Modulations Over Two-Symbol Observation Intervals for the Flat Rician Fading Channel

We consider the differential phase-shift keying modulation over the flat Rician fading channel with perfect channel model information (PCMI), and derive the two-symbol-observation-interval log-likelihood ratio (LLR) metric from first principles. The work generalizes the previous LLR derivations in [16] – [19] , and demonstrates the necessity of the knowledge of the statistical channel model in the exact LLR computation. Assuming the channel is slowly time-varying, we also propose a simple approximate LLR metric based on the generalized likelihood ratio test (GLRT), which requires only the information of the noise spectral density. The advantage of the newly derived PCMI-LLR metric over the approximate metric and the other LLR metrics in the literature is explained from the information-theoretic perspective via the generalized mutual information. Computer simulations are also provided to demonstrate the superiority of the PCMI-LLR metric in both error rate performance and convergence speed for iterative decoding of turbo and low-density parity-check codes in practical systems. This paper aims to present the fundamental principles of LLR computation, emphasizing the importance of selecting the appropriate metric for iterative decoding over fading channels.

Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders

In this paper, a reverse rate matching method is presented for LTE-Advanced turbo decoders. In LTE-Advanced systems, the turbo codes are highly punctured to achieve high data rate when the channel is reliable. In that case, since only a small part of the input frame memory contains meaningful data, accessing all entries of the memory is redundant. To reduce the meaningless accesses, the proposed reverse rate matching method evaluates whether each code bit is punctured or not. As a result, more than 30% of the power consumed in accessing the input memory can be saved when the code rate is high. Furthermore, a low-complexity hardware architecture realizing the proposed method is presented for parallel-SISO decoding. By making use of a specific relationship resident in parallel input indexes, the hardware complexity of the reverse rate matching unit is reduced by 44%.

Efficient soft bit estimation for joint iterative multiple‐input multiple‐output detection

In this study, the authors propose a joint iterative detection and decoding (JIDD) method for a turbo coded multiple-input multiple-output (MIMO) system, with a linear order of complexity. Accurate estimation of soft information should be conditioned for excellent performance of the JIDD, but it usually requires an exponential order of complexity. They propose a method which improves the performance of soft interference cancellation minimum mean-squared error (SIC-MMSE) method by increasing the reliability of the soft information utilised for interference cancellation. The proposed method utilises a posteriori probabilities from the MIMO detector as well as a priori probabilities from the turbo decoder, and perform soft minimum mean-squared error filtering for symbol level detection. With this approach, soft information is fully fed into the symbol detection process, and thus the reliability of soft symbol is increased. In addition, they can separate out the bit-level soft estimation process by using a simple linear method. Simulation results show that the proposed method provides substantial complexity reduction, with a bit error rate performance comparable to the conventional SIC-MMSE methods.

Partial iterative decode of turbo codes for on-board processing satellite platform

There is a contradiction between high processing complexity and limited processing resources when turbo codes are used on the on-board processing (OBP) satellite platform. To solve this problem, this paper proposes a partial iterative decode method for on-board application, in which satellite only carries out limited number of iteration according to the on-board processing resource limitation and the throughput capacity requirements. In this method, the soft information of parity bits, which is not obtained individually in conventional turbo decoder, is encoded and forwarded along with those of information bits. To save downlink transmit power, the soft information is limited and normalized before forwarding. The iteration number and limiter parameters are optimized with the help of EXIT chart and numerical analysis, respectively. Simulation results show that the proposed method can effectively decrease the complexity of onboard processing while achieve most of the decoding gain..