Tunneling Field Effect Transistor Circuits Research Articles

Radiation study of TFET and JLFET-based devices and circuits: a comprehensive review on the device structure and sensitivity

All electronic devices when used in a radiation environment undergo significant changes in their electrical properties. It is interesting to explore the effects of radiation, not only on conventional MOSFET devices but also on novel devices like FinFET, Tunneling Field Effect Transistor (TFET), and Junctionless Field Effect Transistor (JLFET). This study presents a systematic review of radiation studies on TFET and JLFET-based devices/circuits. TFET and JLFET have gained popularity in recent days due to their wide use in ultra-scaled designs than conventional CMOS. The effect of radiation on a divergent range of TFET and JLFET devices and circuits is explored. The variations in DC characteristics and electrical parameters under the influence of radiation strikes are analyzed in detail. The radiation effects like Total Ionizing Dose (TID), and Single Event Upset (SEU) are noted for these devices/circuits. The radiation study on different devices shows that these devices are sensitive to Single Event Effect (SEE), steeper Subthreshold Swing (SS), increase in Electron Hole Pair (EHP) production, increase in drain current (ID), and increase in collected charge (QC), decrease in bipolar gain and trans-conductance.

Operational transconductance amplifier designed with nanowire tunnel-FET with Si, SiGe and Ge sources using experimental data

In this paper operational transconductance amplifiers (OTA) were designed with nanowire (NW) tunnel field effect transistors (TFET) with different source materials (Si, SiGe, and Ge) and compared with NW Si MOSFET devices. Lookup tables with experimental data were used to model the transistors and simulate the OTAs. At the same dimensions and transistor efficiency region, the TFET OTAs have larger gain than the MOSFET circuit. The Ge-source TFET OTA presents the highest differential gain (105 dB), followed by the Si TFET (96 dB) and the SiGe-source TFET (90 dB), with the MOSFET presenting the lowest gain (51 dB). However, the MOSFET has the best gain-bandwidth product (GBW) (9.2 MHz) followed by the Ge-source TFET (1.6 MHz), the SiGe-source TFET (900 kHz) and the Si TFET (41 kHz). The second group of OTAs, where the same power consumption was considered and where the gain of the MOSFET OTA and the GBW of the TFETs’ circuits were increased was also studied. The gain of the MOSFET OTA increased to 56 dB, but it is still lower than the TFET circuits (96, 90 and 102 dB for the Si TFET, SiGe-source TFET and Ge-source TFET, respectively). The GBW of the Si TFET, SiGe-source TFET and Ge-source TFET circuits increased to 71 kHz, 1 MHz, and 2 MHz, respectively. Nevertheless, the MOSFET OTA has the best GBW (4.7 MHz) again but being just 2.35 times the GBW of the Ge-source TFET case. Therefore, because of the high gain of the TFETs OTAs, they are indicated for low power, low-frequency applications, with the Ge-source TFET presenting a good compromise between gain and GBW. The circuits’ linearity was also verified, and they demonstrate to be more dependent on bias choices than on the devices themselves.

A tunnel FET compact model including non-idealities with verilog implementation

We present a compact model for Tunnel Field Effect Transistors (TFET), that captures several non-idealities such as the Trap Assisted Tunneling (TAT) originating from interface traps (Dit), along with Verilog-A implementation. We show that the TAT, together with band edge non-abruptness known as the Urbach tail, sets the lower limit of the sub-threshold swing and the leakage current at a given temperature. Presence of charged trap states also contributes to reduced gate efficiency. We show that we can decouple the contribution of each of these processes and extract the intrinsic sub-threshold swing from a given experimental data. We derive closed form expressions of channel potential, electric field and effective tunnel energy window to accurately capture the essential device physics of TFETs. We test the model against recently published experimental data, and simulate simple TFET circuits using the Verilog-A model. The compact model provides a framework for TFET technology projections with improved device metrics such as better electrostatic design, reduced TAT, material with better transport properties etc.

Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction

Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS technologies for digital, analogue and RF designs. However, it has been demonstrated by several researchers that TFET circuits face increased on-state Miller capacitance effect, which leads to poor transient characteristics with large overshoots and undershoots. This would minimise the reliability of TFET circuits though energy efficient. This work gives more design insights (optimal sizing, number of stages, supply voltage) into TFET circuit reliability and proposes a TFET based circuit interaction design approach for ultra-low power and reliable ring oscillator circuit design. It has been shown that TFET circuit designs without proper reliability enhancement techniques such as circuit interaction or co-design approach exhibits very large undershoots/overshoots (∼20–50%). The proposed TFET circuit co-design approach (i.e. differential topology based design in comparison with the complementary static TFET logic designs) enhances the TFET circuit reliability by minimising the undershoots/overshoots to less than 0.5% with a trade-off in operating frequency and power consumption.

Design guidelines to achieve minimum energy operation for ultra low voltage tunneling FET logic circuits

A tunneling field effect transistor (TFET) attracts attention, because TFET circuits can achieve better energy efficiency than conventional MOSFET circuits. Although design issues in ultra low voltage logic circuits, such as the minimum operatable voltage (VDDmin), have been investigated for MOSFET’s, VDDmin for TFET’s have not been discussed. In this paper, VDDmin of TFET logic circuits is evaluated for the first time and a closed-form expression of VDDmin is derived, which indicates that the within-die threshold voltage variation (σVT) strongly affects VDDmin. In addition, since it is not clear how much the energy of the logic circuits is quantitatively reduced when both the subthreshold swing (S) and the power supply voltage are reduced, an analytical equation of the minimum energy of TFET logic circuits is also derived. From the derived equations, the design guideline is presented for the device engineers of TFET’s that σVT should be reduced as S decreases.

A compact model for tunnel field-effect transistors incorporating nonlocal band-to-band tunneling

To enable circuit design using tunnel field-effect transistors (TFETs), a physics-based model based on nonlocal band-to-band tunneling is developed. To maintain accuracy, the tunneling lengths are estimated assuming that both vertical and horizontal tunneling paths exist in the device. The static current-voltage characteristics are modeled, including the diode currents and Esaki tunneling. Parasitic capacitances and resistances are included to enable transient circuit analyses. The model is validated by comparison with measurements of silicon TFETs, as well as with semiconductor device simulations based on nonlocal band-to-band tunneling. The model accounts for TFET behavior in circuits, as demonstrated by simulations of inverters and static random access memories. Consequently, the model can be used to develop TFET circuits for low-power applications.