TSV Size Research Articles

Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth Memory Applications

The stress of TSV with different dimensions under annealing condition has been investigated. Since the application of TSV and bonding technology has demonstrated a promising approach for vertical connection in HBM stacking, the stress caused by Cu TSV substrates needs to be carefully investigated. The changing in TSV size under the same TSV aspect ratio does not obviously affect the stress toward the surroundings. On the other hand, the adjustment on TSV aspect ratios results in different stress values, and the aspect ratio of 1:8 results in the largest stress in the analysis. Besides, the annealing temperature has more influence on the stress than the size of TSV. As a consequence, reduction on the annealing temperature is an effective method to achieve a low stress for TSV in HBM stacks. Therefore, several methods for low temperature hybrid bonding have also been reviewed and discussed.

Advanced barrier and seed layer deposition enabling multiple type of TSVs integration

TSV integration is a key technology allowing heterogeneous devices 3D integration. However, depending on the targeted application, various TSV sizes and integration schemes exist, all requesting very high aspect ratio. The most common integration is the Mid-process TSV for which aspect ratio is required to be higher than 10:1 whatever application. In the case of large interposers, silicon thickness has to be increased to limit the deformation of the substrate due to highly stressed devices. Same requirements are made by photonic interposers which use thick SOI substrate leading to high warpage during integration. In the opposite, imagers requires to save silicon surface thus reduce TSV size and keep out zone. Silicon thickness has to be kept in the 100 μm range leading then the aspect ratio of the TSV to increase. Recently, Hybrid bonding progresses allowed a new type of TSV to be introduced : High Density TSVs for imagers. In this application, micrometer range TSV have to be filled with a Silicon thickness reduction limited to 10 μm by grinding process control. In order to allow the metal filling of all those type of structures, we have developed a highly conformal barrier and seed layer processes using standard materials for easier integration. The process is based on the use of MOCVD TiN as a barrier. This material is deposited using TDMAT precursor which allows low temperature deposition (200 °C)[1] which extends also the polyvalence of the process toward polymer bonded integrations. The very high step coverage of this process, reported at more than 30% in 20:1 aspect ratio coupled to high resistance to copper diffusion allows as thin as 20 nm barrier thickness which appears relevant economically (for deposition and CMP) and for stress consideration, compared to the well known but thicker PVD TaN process. Considering seed layer, the eG3D process[2] was brought to a high maturity allowing it to be integrated in an applied material raider tool coupled to TSV filling reactors. This process, based on electrografting of copper has already proved a step coverage of more than 50% in 12:1 aspect ratio structures. The presented work shows that the same process requires only deposition parameters change to be able to fully cover 10×150 μm Mid-process TSV as well as 1×10 μm High density ones. The excellent step coverage of this process allowed as thin as 200 nm (for 10×120 μm TSVs) and 100 nm (for (1×10 μm ones) deposited thicknesses to ensure perfect coverage of the structures. eG3D process also has the ability to be used as a repair process for non-continuous widely used PVD Cu seed layers but also be deposited directly on the barrier material. These 2 layers were evaluated together in a 300mm TSV integration schemes of both 10×120 mid process and 1×10 μm High Density structures and qualified electrically. The paper will discuss the deposition process development leading to simultaneously allow copper filling of the very wide range of TSVs on the same process equipment and using the same chemicals. We will then present integration results as well as electrical test of TSV daisy chains of both mid and High density TSVs showing excellent yield for all TSV size and integration schemes.

Stack-through silicon via dynamic power consumption optimization in three-dimensional integrated circuit

Stack-through silicon via (TSV) used in three-dimensional integrated circuit has good temperature and heat transfer characteristics. A novel model for optimizing the dynamic power consumption based on stacked-TSV is proposed in this paper, in which delay, area and minimum aperture are comprehensively considered. After extracting single TSV parasitic electrical parameters, we analyze the influences of TSV size on multilayer TSV power consumption and delay performance, thereby building the hierarchical reduction TSV structure step by step. Moreover, the influences of TSV height and thickness of oxide layer are discussed. Results show that the model can significantly improve the dynamic power consumption at the expense of little delay. The power consumption optimization reduction is up to 19.52% with 5% delay penalty.

Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits

3-D integrated circuits (3-D ICs) offer performance advantages due to their increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the vertical direction. However, the lateral thermal blockage effect becomes increasingly important for TSV via farms (a cluster of TSV vias used for signal bus connections between layers) because the TSV size and pitch continue to scale in μm range and the metal to insulator ratio becomes smaller. Consequently, dense TSV farms can create lateral thermal blockages in thinned silicon substrate and exacerbate the local hotspots. In this paper, we propose a thermal-aware via farm placement technique for 3-D ICs to minimize lateral heat blockages caused by dense signal bus TSV structures. By incorporating thermal conductivity profile of via farm blocks in the design flow and enabling placement/aspect ratio optimization, the corresponding hotspots can be minimized within the wire-length and area constraints.

Electrical Demonstration of TSV Interconnects and Multilevel Metallization for 3D Si Interposer Applications

A TSV test vehicle lot and 3D interposer demonstration lot were successfully fabricated and tested. Fabrication of the TSV test vehicle was accomplished using three process (mask) levels – front-side metal, backside TSV, and backside metal. The TSVs were formed using a vias-last approach with a nominal TSV size of 100μm, and an aspect ratio of 6:1. DRIE bottom clear process conditions were tested which produced 100 % yield on TSV contact chains with up to 540 vias. In addition, optimum process conditions resulted in a TSV resistance of 29 mΩ, and sufficient TSV isolation resistance (> 1MΩ) for the target application. The interposer demonstration lot incorporated five front-side metal levels, one TSV level, and two backside metal levels. The first four metal layers (M1-M4), utilized 2μm Cu and 2μm oxide layers. Metal layers M2-M4 were fabricated using a self-aligned dual damascene process. Each wafer in the demonstration lot had 4 MLM contact chain test structures, with 26400 vias per structure. On two wafers, 100 % yield was achieved on the MLM contact chains. For the dual damascene levels, average contact resistance per via was 4 mΩ. Functional testing was performed on two die from the demonstration lot (die size = 4 cm X 3.7 cm). Over 99 % of the functional nets (circuit paths) passed. Yield on large area test capacitors, tested at wafer level, exceeded 80 %.