TSV Etch Research Articles

Spectroscopic Reflectometry for Optimizing 3D Through-Silicon-Vias Process

The main challenges in 3D metrology involve measuring TSVs etched with very high aspect ratios, where the via depth to diameter ratio approaches 10:1–20:1. In this paper, we introduce an innovative approach to enhance our in-house spectroscopic reflectometer module by integrating aperture technology, resulting in a substantial amplification of interference signals. Our system offers the flexibility to conduct measurements on an average number of TSVs, individual TSVs, or specific periodic arrays of TSVs. Additionally, we demonstrate the utility of the spectroscopic reflectometer as a non-destructive, high-speed metrology solution for in-line monitoring of TSV etch uniformity. Through a series of experimental trials in a reactive ion etch (RIE) process, we show that leveraging feedback data from the reflectometer leads to marked improvements in etch depth uniformity.

Cost Analysis of TSV Process and Scaling Options

SEMATECH evaluated the impact of various process options on the overall manufacturing cost of a TSV module, from TSV lithography and etch through post-plate CMP. The purpose of this work was to understand the cost differences of these options in order to identify opportunities to significantly reduce cost. Included in this study were multiple process and materials options for TSV etch, liner, and barrier/seed (B/S). For each of these options, recipes were adjusted for post-etch clean, ECD Cu fill and CMP overburden, and the resulting cost impacts were evaluated. The TSV dimensions used in this study are 5x50 μm and 2x40 μm. These cost comparisons included a sensitivity analysis, highlighting the main factors responsible for the differences. Cost of materials, tool cost, and throughput were the primary factors affecting cost differences, especially in barrier/seed deposition. In some cases the contributions from both these sources were comparable. We explain the assumptions used and some of the uncertainties inherent in this work. For example, where materials costs were significant, we extrapolated the cost of new materials from research quantities to those needed to support high volume manufacturing. We had to estimate throughputs and materials costs using our best engineering judgment, because the recipes have not yet been optimized. We also considered that the tools used on some non-critical steps might be fully depreciated, or a lower cost tool such as is used in wafer level packaging. Despite these uncertainties and assumptions, we were able to extract some fairly clear conclusions. The process options include the following B/S variations: For 5x50 μm TSVs, the B/S film structure is TaN/Ta/Ru/Cu, and the options are with and without the Ru and/or Cu layers. For 2x40 μm TSVs, the B/S structure is TaN/Ru/Cu, with different thicknesses of Ru, and the Cu is an optional seed layer for the field. We also discuss the impact of scaling the TSV dimensions on manufacturing costs. This work is continuing to look at different process options and to apply this methodology to MEOL modules such as temporary bond and debond, wafer thinning, and TSV reveal.

Multi-scale X-ray tomography for process and quality control in 3D TSV packaging

Advanced packaging processes and the resulting 3D products challenge process and quality control. X-ray imaging and X-ray computed tomography (XCT) provide non-destructive characterization capabilities on specimens across a range of length scales, observing features with sizes spanning from millimeters over micrometers down to several 10 nanometers. They are the techniques of choice for two- or three-dimensional inspection of medium and small sized objects with a resolution down to several 10 nm. In this paper, the potential and the limits of XCT for process development, process monitoring, and failure analysis in 3D TSV stacks are described. It is shown that a multi-scale approach, i.e. using imaging techniques with several resolution ranges, is necessary for these particular tasks. Since sub-micron XCT and nano XCT are very useful techniques with a promising prospect for the future, we focus on the capabilities of two lab-based XCT tools with sub-micron resolution (Zeiss Versa) and with < 50 nm resolution (Zeiss Ultra). We demonstrate the capabilities for nondestructive imaging of multi-die stacks with TSVs and AgSn microbumps. Major filling defects in TSVs are clearly visualized. An analysis of individual bumps reveals mismatches in relative positioning, micron-size pores, and the distribution of intermetallic phases. This information provides important information regarding the respective process steps (process control) and the product quality (quality control). In addition, TSV etch profiles and small voids in Cu TSVs are visualized. Since deviations from the targeted geometry and defects are difficult to locate precisely from a two-dimensional image, X-ray computed tomography has to be applied.

Optimized TSV Module for High Performance 2.5D Device Packaging

3D-IC has been increasingly adopted by the industry owing to its promise of higher device speed and package bandwidth, improved power consumption, reduced form factor, and lower cost for important applications over a wide range of industrial segments including image sensors, logic-memory and logic-logic integration, MEMS, integrated optical interposers and LEDs. This presentation is a systematic study of multiple experimental factors affecting the electrical performance, reliability and scalability of TSVs. Electrical modeling and simulation was used to determine the key factors influencing singal transmission and return losses in TSVs at high (>1 GHz) frequencies. A variety of process modules and steps for the fabrication of through silicon vias were then systematically optimized to ensure high performance. The modules evaluated include TSV etch, TSV fill, chemical mechanical polishing (CMP), pad finish, bonding schemes, wafer thinning, via reveal, passivation, wiring and bumping. One example is the improvement of TSV profile and sidewall roughness through the optimization of DRIE parameters and wet chemical methods to reduce silicon sidewall roughness from that of a typical Bosch etch to less than 10nm which is critical for adhesion of barrier/seed layer and the final reliability of 2.5D packaging. Scalability of void-free via fill process with respect to TSV diameter and depth was addressed by using highly conformal barrier layers. Adhesion of Cu to the barrier layer was also improved upon detailed analysis to prevent delamination and improve reliability. A bottom up plating chemistry with significantly low impurity content was utilized to mitigate voids, seams and excessive overburden in the TSV. Its impact on stress and delamination issues and subsequent reliability failures was studied in details. The annealing process following TSV formation is systematically studied with varying conditions and characterized with metrology and electrical tests to investigate its effect on microstructure and material properties. The process parameters were tuned for CMP of Cu, adhesion and barrier layer without causing corrosion or delamination between adjacent layers. Process requirements for these modules in TSV process are closely related. This presentation will review the process module development in the context of their effects on the integrated TSV parameters (performance, reliability and scalability). We will also provide an in-depth discussion on process module optimization, electrical and mechanical characterization and cost reduction methodologies.

(Invited) Technologies and Challenges of Fine Pitch Backside Via-Last TSV Process Integration for 3DIC Applications

TSV based 3D stacking IC technology has been aggressively studied recently because of strong benefits in terms of significantly form factor shrinkage, superior system performance (bandwidth & speed), great power reduction, and heterogeneous integration capability. According to different applications, there are different integration options for TSV processing. For high performance 3D system applications which required fine TSV pitch and massive IO connections, how to establish a proper TSV integration scheme became a key importance of enabling 3D IC commercialization. In additional to common foundry used via-middle (VM) process, two another via last approaches, either forming TSV form front-side or backside were also been considered as major TSV process schemes. Although front-side via last (FVL) TSV is widely adopted by OSATs, this scheme is inherently not suitable for fine pitch and high density TSV applications because of significant area penalty and wire routing constraint comparing to VM TSV process. Another backside via last (BVL) TSV process, however, showed many advantages over common VM TSV process while achieving same TSV scalability/density and routing flexibility. For examples: (1) Cu TSVs of BVL were formed after completely CMOS FEOL+BEOL processes, thus it is naturally much less or no Cu pumping out induced yield loss issues comparing to VM process; (2) BVL TSV etching can be stopped on front-side metal 1 layer instead of time etching in blind TSV of VM scheme; (3) No complicated and yield sensitive backside Cu reveal issue were involved; (4) TSV & RDL can be formed together via dual-damascene like processing to simplify process flow and reduce cost of ownership; (5) BVL process can be adopted by either foundry or OSAT manufacturers resulting in most flexible business model in 3DIC supply chain. Despite of the vantage of backside via-last scheme, many process challenges still need to be solved. In this paper, key issues of via middle integration were briefly reviewed. A capable of high aspect ratio and fine pitch TSV (CD … 5um) manufacture scheme was proposed via backside via last integration scheme. Key process technologies and challenges of this BVL scheme, such as temporary bonding, glue material selection, wafer thinning, backside TSV formation, CMP planarization as well as cost reduced TSV/RDL dual damascene flow are investigated.

ESH Friendly Solvent for Stripping Positive and Negative Photoresists in 3D-Wafer Level Packaging and 3D-Stacked IC Applications

NMP is a commonly used solvent for removing positive photoresist in 3D applications, especially in electroplating and (micro-) bumping. However, the negative photoresists are more and more preferred in these applications. Unfortunately, NMP is inefficient for negative photoresist and it is not considered in Europe as an ESH solvent anymore. In this paper a comparative study was carried out in order to identify a solvent that is ESH friendly and a one-size-fits-all solution for stripping negative-tone and thick positive-tone photoresist (2-22 μm) for (micro-) bumping, electroplating and TSV etch applications. The study was performed at tool level.

Solution for HVM TSV Etch Process

As the industry is getting their hands around processes critical to cost-effective and reliable TSV manufacturing a key enabler is process control through inspection and metrology. In working with the industry, Rudolph has developed a suite of solutions that incorporate inspection, metrology and software enabling rapid yield ramp. The solution set apply all the way from via etch to CMP, RLD, micro-bumping and all the way to Chip on Wafer mount and post-saw. Within the TSV process a challenging inspection is that of detecting defects after CMP and nail reveal. The bonded wafers are warped, there are no alignment fiducials and the resolution requirement is high. Rudolph has developed a specific solution designed to address the nail reveal defectivity issue.

A Novel TSV Etching using NLD and VHF CCP Plasma For 3-D Stacked Devices.

In this study, the etch development of high etch rate and high aspect ratio for the fabrication of various diameters of thru silicon via is described. There are a lot of applications about TSV's methods. There TSV need to meet strict requirements with respect to high etch rate, sidewall roughness and undercut. For diameter of vias down to 10um a SiO2 hard mask based SF6/O2 etch approach is used by magnetic neutral loop discharge plasma (NLD plasma). This system can be used for oxide etching and Si etching. In the case of oxide etching, some magnetic coil currents are applied to generate magnetic neutral loop in the vacuum chamber in order to high density plasma in the low pressure below 1 Pa. On the other hand, in the case of Si etching, the pressure is raised up to 2∼10 Pa. As a result, an etched profile of TSV with diameter of 1.5 um and the etched depth of 11.5 um, aspect ratio is 7.6, was achieved. The etch rate is about 4.5 um/min. For diameter of vias up to 10um, a resist mask based and SF6/O2 etch approach is also used by very high frequency coactivity coupled plasma. VHF CCP etching system was used to high-pressure process, more than 50Pa, as a purpose to high etch rate of up to 10um pattern's TSV etching. As a result, a vertical profile of TSV with diameter of 50 um and the etched depth of 50 um, aspect ratio is 1.0, was achieved. The etch rate is about 45 um/min. NLD and VHF CCP processes are non-cycle etch methods, and to successfully smooth pattern TSV.