The TRON project that originated at the University of Tokyo covers all aspects of an open computer system, from the CPU to the operating system and user interface. The TRON architecture does not follow the current trend toward highly regular, streamlined RISC architectures. Instead, the TRON CPU specifies a complex architecture with a sophisticated addressing mechanism. Hitachi has produced a versatile 16/32-bit microprocessor, the H16, that is loosely compatible with the TRON specification. Details of the H16 are included in this application note, which has been selected because the H16 has many interesting features not shared by many of its 16-bit predecessors. Besides its complex addressing modes, it has up to 16 banks of 32-bit general-purpose registers. These banks can be used to implement high-speed context switching in multitasking or interrupt-driven systems. A second mode of operation allows high-speed function procedure calls for efficient high-level language execution. Not content with providing a powerful CPU, Hitachi has included several peripherals on chip which make it easier to design a single-board microcomputer with a minimal component count. In addition to the conventional serial port, timer/counter, and the DMA controller, the H16 has a programmable wait-state generator and built-in programmable address decoder.
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