Triple Patterning Lithography Research Articles

Discrete relaxation method for hybrid e-beam and triple patterning lithography layout decomposition

Hybrid electron beam lithography (EBL) and triple patterning lithography (TPL) is an advanced technology for IC manufacture. To solve the hybrid EBL and TPL layout decomposition problem (HETLD), we propose a discrete relaxation method in this paper. Existed works hard to evaluate the quality of the obtained results theoretically. Our discrete relaxation is the first approach which can be used to evaluate the solution quality. First, we introduce an extended minimum weight dominating set coloring problem (EMDSC). We show that the EMDSC problem is a discrete relaxation of the HETLD problem, which is solved by an integer linear programming (ILP) approach. Second, we legalize the relaxation solution to a feasible solution of the initial problem by inserting stitches and assigning EBLs. Experimental results show that our method achieves the near-optimal solution.

Printability Enhancement with Color Balancing for Multiple Patterning Lithography

Due to the delay of Next Generation Lithography technologies, multiple patterning lithography (MPL) is still the major solution for the continuous advance of process nodes. Considering pattern color (density) balancing on multiple masks during layout decomposition is crucial to reduce pattern distortion and lithographic hotspots. While most of previous studies consider global color balancing during layout decomposition, we propose the first work of post-decomposition local color uniformity optimization, which will contribute to better pattern printability. In our flow, a linear programming (LP) formulation is developed to derive a good initial solution, and then a simulated annealing (SA)-based algorithm is proposed to globally search optimal solutions. Finally, a solution refinement procedure is applied based on the FM partitioning heuristic. The proposed flow is suitable for general MPL with an arbitrary number of masks, and we respectively demonstrate its effectiveness on double patterning lithography (DPL) and triple patterning lithography (TPL). The former indicates that our flow can derive near-optimal solutions, and the latter shows about 29 percent improvement over a state-of-the-art color balancing-aware TPL decomposer.

Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration

In 10nm technology node, self-aligned double patterning (SADP) and triple patterning lithography (TPL) allow us to achieve minimum wiring pitch of around 45nm. While metal layers can be printed by SADP, via layer manufacturing requires TPL to maintain design rules. SADP-aware detailed routing is proposed to ensure decomposability of metal layer patterns. However, its routing solution does not automatically guarantee TPL decomposable via layers. Vias have an inherently low reliability and via failure causes a great yield loss. Double via insertion (DVI) is an effective means to increase yield by reducing via failures. With the restriction of SADP design rules and consideration of TPL decomposability for via layers, DVI becomes a more challenging problem. In this paper, we consider DVI and via layer TPL manufacturability simultaneously in SADP-aware detailed routing. Both spacer-is-metal and spacer-is-dielectric types of SADP are considered. Furthermore, we tackle the TPL-aware DVI in postrouting stage. Both ILP and high-performance heuristic solutions are proposed. The experimental results demonstrate our router can obtain 100% routability and TPL decomposable via layers with reduced dead via count. Meanwhile, compared with the ILP approach to solve TPL-aware DVI problem, the heuristic approach can achieve similar solution quality and significant speedup.

Discrete relaxation method for contact layer decomposition of DSA with triple patterning

Block copolymer directed self-assembly (DSA) is a simple and promising candidate next-generation device fabrication technology, which is low-cost as complement with multi-patterning for contact layer patterning. In this paper, we consider the contact layer mask and template assignment problem of DSA with triple patterning lithography of general layout. To address this problem, first we construct a weighted conflict grouping graph, in which edges with negative weights are introduced, then a discrete relaxation based mask assignment problem is proposed. The integer linear program (ILP) formulation of the discrete relaxation problem is solved for obtaining a lower bound on the optimal value of this problem. In order to improve the lower bound, some valid inequalities are introduced to prune some poor relaxation solutions. At last, the obtained discrete relaxation solution is transformed to a legal solution of the original problem by solving a template assignment problem on the layout graph, which provides an upper bound on the optimal value of the original problem. Experimental results and comparisons show the effectiveness and efficiency of our method. In addition, under the discrete relaxation theory, the quality of our experimental results can be evaluated by the obtained upper and lower bounds. Specifically, the gap between the obtained upper and lower bounds is 0 for most of the sparse benchmarks, and the average gap is 0.4% for dense benchmarks.

Two-Stage Layout Decomposition for Hybrid E-Beam and Triple Patterning Lithography

Hybrid e-beam lithography (EBL) and triple patterning lithography (TPL) are advanced technologies for the manufacture of integrated circuits. We propose a technology that combines the advantages of EBL and TPL, which is more promising for the pattern product industry. Layout decomposition is a crucial step in this technology. In this article, we propose a two-stage decomposition flow for the hybrid e-beam and triple patterning lithography of the general layout decomposition (HETLD) problem. At the first stage, we formulate two optimization problems: the e-beam and stitch-aware TPL mask assignment (ESTMA) problem and the extended minimum weight dominating set for R 4 mask assignment (MDS R 4 MA) problem. Binary linear program formulations of the two problems are solved by the cutting plane approach. At the second stage, solutions of the first stage problems are legalized to feasible solutions of the HETLD problem by stitch insertion and e-beam shot. To speed up decomposition, we reduce the problem size by removing some vertices and some minor conflict edges before decomposition. Experimental results show the effectiveness of our decomposition methods based on ESTMA and MDS R 4 MA.

A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning

Self-aligned triple patterning (SATP) lithography is one of the most promising technologies for next-generation semiconductor manufacturing process. Self-aligned patterning attracts much interest because of its significant advantage over the litho-etch-litho-etch patterning in reducing the overlay problem in lithography. However, pattern decomposition in SATP is challenging due to its counterintuitive mask synthesis. It remains relatively unstudied and its practical solutions remain to be proposed. This paper proposes an effective algorithm for SATP layout decomposition without grid-based quantization and thus substantially reduces the number of variables and constraints in solution search. Boolean satisfiability (SAT) and integer linear programming (ILP) are exploited for efficient computation. In addition to deriving high-quality layout decomposition solutions with overlay minimization, our method also allows nondecomposable spot identification to facilitate layout rectification. Experimental results demonstrate the superiority of our method compared to prior work and show the relative advantages of SAT and ILP formulations.

Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict

Triple patterning lithography (TPL) is one of the most promising lithography technology in sub-14-nm technology nodes, especially for complicated low metal layer manufacturing. To overcome the intracell routability problem and improve the cell regularity, recently middle-of-line (MOL) layers are employed in standard cell design. However, MOL layers may introduce a large amount of cross-row TPL conflicts for row-based design. Motivated by this challenge, in this paper we propose the first TPL aware detailed placement toward zero cross-row MOL conflict. In standard cell precoloring, Boolean-based look-up table is proposed to reduce solution space. In detailed placement stage, three powerful techniques, i.e., local reordered single row refinement, min-cost flow-based conflict removal, and local cell interleaving, are proposed to provide zero TPL conflict solution. The experimental results demonstrate the effectiveness of our proposed methodologies.

Discrete Relaxation Method for Triple Patterning Lithography Layout Decomposition

In this paper, we consider the triple patterning lithography layout decomposition problem. To address the problem, a discrete relaxation theory is built. For designing a discrete relaxation based decomposition framework, we propose a surface projection method for identifying native conflicts in a layout, and then constructing the conflict graph. Guided by the theory, the conflict graph is reduced to small size subgraphs by vertex removals, which is a discrete relaxation. Furthermore, by ignoring stitch insertions and assigning weights to features, the layout decomposition problem on the small subgraphs is further relaxed to a 0-1 program, which is solved by the Branch-and-Bound method. To obtain a feasible solution of the original problem, legalization methods are introduced to legalize a relaxation solution. At the legalization stage, we prior utilize one-stitch insertion to eliminate conflicts, and use a backtrack coloring algorithm to obtain a better solution. We test our decomposition approach on the ISCAS-85 & 89 benchmarks. Comparisons of experimental results show that our approach finds solutions of some benchmarks better than those by the state-of-the-art decomposers. Especially, according to our discrete relaxation theory, some optimal decompositions are obtained.

Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs

Triple patterning lithography (TPL) is regarded as a promising technique to handle the manufacturing challenges in the 14nm technology node and beyond. It is necessary to consider TPL in early design stages to make the layout more TPL friendly and reduce the manufacturing cost. In this paper, we propose a flow to co-optimize cell layout decomposition and detailed placement. Our cell decomposition approach can enumerate all coloring solutions with the minimum number of stitches. The experimental results show that our approach can outperform the existing work in all aspects of stitch number, half-perimeter wirelength (HPWL), and running time. We further extend our placer to consider the displacement of cells as a constraint and as an objective, respectively, which can help to preserve the quality of the input placement. Effectiveness of the extensions is verified by the experiments.

Yield-aware mask assignment by positive semidefinite relaxation in triple patterning using cut process

LELECUT type triple patterning lithography is one of the most promising techniques in 14 nm logic node and beyond. To prevent yield loss caused by overlay error, LELECUT mask assignment, which is tolerant to overlay error, is desired. We propose a method that obtains a LELECUT assignment that is tolerant to overlay error. The proposed method uses positive semidefinite relaxation and randomized rounding technique. In our method, the cost function that takes the length of boundary of features determined by the cut mask into account is introduced.

Systematic framework for evaluating standard cell middle-of-line robustness for multiple patterning lithography

For robust standard cell design, designers need to improve the intercell compatibility for all combinations of cells and cell placements. Multiple patterning lithography colorability check breaks the locality of traditional rule check, and N-wise checks are strongly needed to verify the colorability for layout interactions across cell boundaries. A systematic framework is proposed to evaluate the library-level robustness over multiple patterning lithography from two perspectives, including complete checks on two-row combinations of cells and long-range interactions. With complete checks on two-row combinations of cells, the vertical and horizontal boundary checks are explored to predict illegal cell combinations. For long-range interactions, random benchmarks are generated by cell shifting and tested to evaluate the placement-level efforts needed to reduce the manufacturing complexity from quadruple patterning lithography to triple patterning lithography for the middle-of-line (MOL) layers. Our framework is tested on the MOL layers but can be easily adapted to other critical layers with multiple patterning lithography constraints.

Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography

In this article we present a pairwise coloring (PWC) approach to tackle the layout decomposition problem for triple patterning lithography (TPL). The main idea is to reduce the problem to a set of bi-coloring problems. The overall solution is refined by applying a bi-coloring method for pairs of color sets per pass. One obvious advantage of this method is that the existing double patterning lithography (DPL) techniques can be reused effortlessly. Moreover, we observe that each pass can be fulfilled efficiently by integrating an SPQR-tree-graph-division-based bi-coloring method. In addition, to prevent the solution getting stuck in the local minima, an adaptive multi-start (AMS) approach is incorporated. Adaptive starting points are generated according to the vote of previous solutions. The experimental results show that our method is competitive with other works on both solution quality and runtime performance.

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography

As the feature size of semiconductor process further scales to sub-16 nm technology node, triple patterning lithography (TPL) has been regarded as one of the most promising lithography candidates along with extreme ultraviolet, electron beam lithography, and directly self-assembly. M1 and contact layers, which are usually deployed within standard cells, are the most critical and complex parts for modern digital designs. Traditional design flow that ignores TPL in early stages may limit the potential to resolve all the TPL conflicts. In this paper, we propose a coherent framework, including standard cell compliance and detailed placement, to enable TPL friendly design. Considering TPL constraints during early design stages, such as standard cell compliance, improves the layout decomposability. With the precoloring solutions of standard cells, we present a TPL aware detailed placement where the layout decomposition and placement can be resolved simultaneously. In addition, we propose a linear dynamic programming to solve TPL aware detailed placement with maximum displacement, which can achieve good trade-off in terms of runtime and performance. Experimental results show that our framework can achieve zero conflict, meanwhile can effectively optimize the stitch number and placement wire-length.

On Refining Row-Based Detailed Placement for Triple Patterning Lithography

In this paper, we study row-based detailed placement refinement for triple patterning lithography (TPL), which asks to find a refined detailed placement solution as well as a valid TPL layout decomposition under the objective of minimizing the number of stitches and the half-perimeter wirelength. Our problem does not have precoloring solutions of cells as the input, and it allows using techniques, including white space insertion, cell flipping, adjacent-cell swapping, and vertical cell movement, to optimize the solution quality. We first present (resource-constrained) shortest-path-based algorithms for several TPL-aware single-row placement problems that allow or disallow perturbing a given cell ordering. Based on these algorithms, we then propose an approach to our TPL-aware detailed placement refinement problem, which first minimizes the number of stitches and then minimizes the wirelength. Finally, we report extensive experimental results to demonstrate the effectiveness and efficiency of our approach.

Layout Decomposition for Triple Patterning Lithography

As minimum feature size and pitch spacing further scale down, triple patterning lithography is a likely 193 nm extension along the paradigm of double patterning lithography for 14-nm technology node. Layout decomposition, which divides input layout into several masks to minimize the conflict and stitch numbers, is a crucial design step for double/triple patterning lithography. In this paper, we present a systematic study on triple patterning layout decomposition problem, which is shown to be NP-hard. Because of the NP-hardness, the runtime required to exactly solve it increases dramatically with the problem size. We first propose a set of graph division techniques to reduce the problem size. Then, we develop integer linear programming (ILP) to solve it. For large layouts, even with the graph-division techniques, ILP may still suffer from serious runtime overhead. To achieve better trade-off between runtime and performance, we present a novel semidefinite programming (SDP)-based algorithm. Followed by a mapping process, we can translate the SDP solutions into the final decomposition solutions. Experimental results show that the graph division can reduce runtime dramatically. In addition, SDP-based algorithm can achieve great speed-up even compared with accelerated ILP, with very comparable results in terms of the stitch number and the conflict number.

Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

Triple patterning lithography layout decomposition using end-cutting

Triple patterning lithography (TPL) is one of the most promising techniques in the 14-nm logic node and beyond. Conventional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently, as an alternative process, TPL with end-cutting (LELE-EC) was proposed to overcome the limitations of LELELE manufacturing. In the LELE-EC process, the first two masks are LELE type double patterning, while the third mask is used to generate the end-cuts. Although the layout decomposition problem for LELELE has been well studied in the literature, only a few attempts have been made to address the LELE-EC layout decomposition problem. We propose a comprehensive study for LELE-EC layout decomposition. Layout graph and end-cut graph are constructed to extract all the geometrical relationships of both input layout and end-cut candidates. Based on these graphs, integer linear programming is formulated to minimize the conflict and the stitch numbers. The experimental results demonstrate the effectiveness of the proposed algorithms.

A Novel Layout Decomposition Algorithm for Triple Patterning Lithography

While double patterning lithography (DPL) has been widely recognized as one of the most promising solutions for the sub-22 nm technology node to enhance pattern printability, triple patterning lithography (TPL) will be required for gate, contact, and metal-1 layers which are too complex and dense to be split into only two masks, for the 15 nm technology node and beyond. Nevertheless, there is very little research focusing on the layout decomposition for TPL. Recent work proposed the first systematic study on the layout decomposition for TPL. However, the proposed algorithm extending a stitch-finding method used in DPL may miss legal stitch locations and generate conflicts that can be resolved by inserting stitches for TPL. In this paper, we point out two main differences between DPL and TPL layout decompositions. Based on the two differences, we propose a novel TPL layout decomposition algorithm. We first present two new graph reduction techniques to reduce the problem size without degrading overall solution quality. We then propose a stitch-aware mask assignment algorithm, based on a heuristic that finds a mask assignment such that the conflicts among the features in the same mask are more likely to be resolved by inserting stitches. Finally, stitches are inserted to resolve as many conflicts as possible. Experimental results show that the proposed layout decomposition algorithm can achieve around 56% reduction of conflicts and more than 40X speed-up, as compared to the previous work.