Triple Modular Redundancy Research Articles

Improving Fault Tolerance for FPGA SoCs through Post-Radiation Design Analysis

FPGAs have been shown to operate reliably within harsh radiation environments by employing single-event upset (SEU) mitigation techniques, such as configuration scrubbing, triple-modular redundancy, error correction coding, and radiation aware implementation techniques. The effectiveness of these techniques, however, is limited when using complex system-level designs that employ complex I/O interfaces with single-point failures. In previous work, a complex SoC system running Linux applied several of these techniques only to obtain an improvement of 14 \(\times\) in mean time to failure (MTTF). A detailed post-radiation fault analysis found that the limitations in reliability were due to the DDR interface, the global clock network, and interconnect. This article applied a number of design-specific SEU mitigation techniques to address the limitations in reliability of this design. These changes include triplicating the global clock, optimizing the placement of the reduction output voters and input flip-flops, and employing a mapping technique called “striping.” The application of these techniques improved MTTF of the mitigated design by a factor of 1.54 \(\times\) and thus provides a 22.8X \(\times\) MTTF improvement over the unmitigated design. A post-radiation fault analysis using BFAT was also performed to find the remaining design vulnerabilities.

Performance Testing of the Triple Modular Redundancy Mitigation Circuit Test Environment Implementation in Field Programmable Gate Array Structures

The logic structures implemented in Field Programmable Gate Arrays (FPGAs) are often critical and their correct operation is vital. FPGA devices are often used in areas where there is increased ionising radiation (space, medical diagnostics, aviation or nuclear power). There is therefore a need for mechanisms to correct radiation-induced errors. A common approach is the redundant implementation of particularly critical parts of the logic structure. By triplicating selected fragments, it is possible not only to detect potential errors but also to correct them. Such an approach is called triple modular redundancy (TMR), and its essence lies in the use of specialised voting circuits called voters, which allow the erroneous results of individual subcircuits to be eliminated by voting. The triplicate circuit under consideration, together with the voter, constitutes the mitigation structure. It becomes necessary to develop a test environment to assess the correct operation of these circuits. Also key is the efficiency of the implementation of these structures, which can be related to the occupation of logical resources or the power consumption of a given implementation. This paper demonstrates the essence of implementing a test environment to test the correctness of the mitigation of logic structures using TMR voters. An error injector mechanism using the Pseudo-Random Bit Sequence (PRBS) register is proposed, which introduces an element of randomness into the testing process. The aim of this research is to determine the implementation efficiency of the proposed test environment. In the experimental part, the implementation costs of the proposed solution were examined. The results indicate that between 66 and 109 LUT blocks were required to implement the error injector, corresponding to a relatively small increase in dynamic power consumption: by 22% for combinational circuits and by 37% for sequential circuits.

FKeras: A Sensitivity Analysis Tool for Edge Neural Networks

Edge computation often requires robustness to faults, e.g., to reduce the effects of transient errors and to function correctly in high radiation environments. In these cases, the edge device must be designed with fault tolerance as a primary objective. FKeras is a tool that helps design fault-tolerant edge neural networks that run entirely on chip to meet strict latency and resource requirements. FKeras provides metrics that give a bit-level ranking of neural network weights with respect to their sensitivity to faults. FKeras includes these sensitivity metrics to guide efficient fault injection campaigns to help evaluate the robustness of a neural network architecture. We show how to use FKeras in the co-design of edge NNs trained on the high-granularity endcap calorimeter dataset, which represents high energy physics data, as well as the CIFAR-10 dataset. We use FKeras to analyze a NN’s fault tolerance to consider alongside its accuracy, performance, and resource consumption. The results show that the different NN architectures have vastly differing resilience to faults. FKeras can also determine how to protect neural network weights best, e.g., by selectively using triple modular redundancy on only the most sensitive weights, which reduces area without affecting accuracy.

Energy-efficient triple modular redundancy scheduling on heterogeneous multi-core real-time systems

Triple modular redundancy (TMR) fault tolerance mechanism can provide almost perfect fault-masking, which has the great potential to enhance the reliability of real-time systems. However, multiple copies of a task are executed concurrently, which will lead to a sharp increase in system energy consumption. In this work, the problem of parallel applications using TMR on heterogeneous multi-core platforms to minimize energy consumption is studied. First, the heterogeneous earliest finish time algorithm is improved, and then according to the given application's deadline constraints and reliability requirements, an algorithm to extend the execution time of the copies is designed. Secondly, based on the properties of TMR, an algorithm for minimizing the execution overhead of the third copy (MEOTC) is designed. Finally, considering the actual situation of task execution, an online energy management (OEM) method is proposed. The proposed algorithms were compared with the state-of-the-art AFTSA algorithm, and the results show significant differences in energy consumption. Specifically, for light fault detection, the energy consumption of the MEOTC and OEM algorithms was found to be 80% and 72% respectively, compared with AFTSA. For heavy fault detection, the energy consumption of MEOTC and OEM was measured at 61% and 55% respectively, compared with AFTSA.

D2D Self Organization in IOT via Triple Modular Redundancy Based MDS Code

Device-to-Device (D2D) communication is a key enabling technology to replace base station-to-device(B2D) communication. D2D with IoT realization has spectral and energy-efficient features for on-time quality data transfer. However, the rapid growth of such networks and the dynamic quality of service demands of user equipment require robust and efficient service quality in disasters, outages, and adversarial conditions. To address this challenge, this paper proposes a triple modular redundancy based on the maximum distance separable (TMR-MDS) technique has been proposed, which modifies the repair bandwidth by utilizing more storage occupation and improving the D2D link availability in the system. The proposed TMR-MDS technique will be used, which is composed of two phases: trust management modules and triple modular redundancy storage modules. As part of the initial stage of trust management, a fuzzy logic model is employed to determine the user’s trust value after the user’s behaviour is examined. Second, using the majority voting scheme to improve triple modular redundancy storage. Furthermore, if any problem occurs in the node, then it will self-organize. MATLAB is used to evaluate the performance of the proposed system. The overall system performance is evaluated in terms of the network’s trust level, and the communication cost of the proposed strategy. As per the experimental results, the proposed TMR-MDS method has a better performance of 12.67%, 23.68%, and 25.87% than hierarchical bi-partite, double replication MDS, and unequal repairing locality code.

Evaluation and Mitigation of Weight-Related Single Event Upsets in a Convolutional Neural Network

Single Event Upsets (SEUs) are most likely to cause bit flips within the trained parameters of a convolutional neural network (CNN). Therefore, it is crucial to analyze and implement hardening techniques to enhance their reliability under radiation. In this paper, random fault injections into the weights of LeNet-5 were carried out in order to evaluate and propose strategies to improve the reliability of a CNN. According to the results of an SEU fault injection, the accuracy of the CNN can be classified into the following three categories: benign conditions, poor conditions, and critical conditions. Two efficient methods for mitigating weight-related SEUs are proposed, as follows: weight limiting and Triple Modular Redundancy (TMR) for the critical bit of the critical layer. The hardening results show that when the number of SEU faults is small, the weight limiting almost completely eliminates the critical and poor conditions of LeNet-5’s accuracy. Additionally, even when the number of SEU faults is large enough, combining the weight limiting and TMR methods for the critical bit of the critical layer can retain the occurrence rate of benign conditions at 98%, saving 99.3% of the hardware resources compared to the Full-TMR hardening method.

Investigating and Reducing the Architectural Impact of Transient Faults in Special Function Units for GPUs

Ensuring the reliability of GPUs and their internal components is paramount, especially in safety-critical domains like autonomous machines and self-driving cars. These cutting-edge applications heavily rely on GPUs to implement complex algorithms due to their implicit programming flexibility and parallelism, which is crucial for efficient operation. However, as integration technologies advance, there is a growing concern regarding the potential increase in fault sensitivity of the internal components of current GPU generations. In particular, Special Function Unit (SFU) cores inside GPUs are used in multimedia, High-Performance Computing, and neural network training. Despite their frequent usage and critical role in several domains, reliability evaluations on SFUs and the development of effective mitigation solutions have yet to be studied and remain unexplored. This work evaluates the impact of transient faults in the main hardware structures of SFUs in GPUs. In addition, we analyze the main overhead costs and benefits of developing selective-hardening mechanisms for SFUs. We focus on evaluating and analyzing two SFU architectures for GPUs (’fused’ and ’modular’) and their relations to energy, area, and reliability impact on parallel applications. The experiments resort to fine-grain fault injection campaigns on an RTL GPU model (FlexGripPlus) instrumented with both SFUs. The results on both SFU architectures indicate that fused SFUs (in commercial-grade devices) require lower area overhead (about 27%) for their integration in GPUs but are more vulnerable to transient faults (in up to 47% for the analyzed cases) and less power efficient (in up to 36.6%) than modular SFUs. Moreover, the reliability estimation shows that Modular SFUs are structurally more resilient than Fused ones in up to one order of magnitude. Similarly, selective-hardening mechanism based on Triple-Modular Redundancy (TMR) shows that coarse-grain strategies might increase the reliability of the overall SFUs under feasible overhead costs.

Cost-effective reliability enhancement for video stitching applications based on error-tolerance

Image (video) stitching technology has been widely used in real-time video applications. In this paper, for the first time, we address design and implementation of a reliable image (video frame) stitching system and focus on its video applications. In particular, we show that by well exploiting the inherent error-tolerability of the image stitching process, a cost-effective reliability enhancement solution can be enabled. For input images (video frames), the proposed system carries out a unique no-reference error detection process where the acceptability of potential errors in input image data can be tested. Particularly, no golden data are required, which greatly facilitates the implementation of an on-line testing process. Based on the testing results, a simple yet effective repair process is enabled for transforming unacceptable stitching results into acceptable ones. Our experimental results show that acceptability testing accuracy of our error detection process achieves 98.4 %. The experimental results on 864,000 various test cases also show that 80 % of the unacceptably erroneous stitched video frames can be successfully repaired, thereby achieving 5× lifetime extension. In addition, when compared to the typical ECC (Error Correcting Code) or TMR (Triple Modular Redundancy) reliability improvement methods, our system not only requires much less hardware cost, but also incurs only ignorable performance overhead. These lead to almost no loss in the achievable FPS (Frame Per Second), and thus real-time video stitching can still be achieved but with high reliability.

First test results of the HGCAL concentrator ASICs: ECON-T and ECON-D

With over 6 million channels, the High Granularity Calorimeter for the CMS HL-LHC upgrade presents a unique data transmission challenge. The ECON ASICs provide a critical stage of on-detector data compression and selection for the trigger path (ECON-T) and data acquisition path (ECON-D) of the HGCAL. The ASICs, fabricated in 65 nm CMOS, are radiation tolerant up to 200 Mrad and require low power consumption: < 2.5 mW/sensor-channel per chip. We report on the first functionality and radiation tests for the ECON-D-P1 full-functionality prototype. We present a comparison of single event effect (SEE) cross sections measured for different methods of triple modular redundancy using test results from the ECON-T-P1 full-functionality prototype.

Implementation of Highly Reliable Convolutional Neural Network with Low Overhead on Field-Programmable Gate Array

Due to the advantages of parallel architecture and low power consumption, a field-programmable gate array (FPGA) is typically utilized as the hardware for convolutional neural network (CNN) accelerators. However, SRAM-based FPGA devices are extremely susceptible to single-event upsets (SEUs) induced by space radiation. In this paper, a fault tolerance analysis and fault injection experiments are applied to a CNN accelerator, and the overall results show that SEUs occurring in a control unit (CTRL) lead to the highest system error rate, which is over 70%. After that, a hybrid hardening strategy consisting of a finite state machine error-correcting circuit (FSM-ECC) and a triple modular redundancy automatic hardening technique (TMR-AHT) is proposed in this paper to achieve a tradeoff between radiation reliability and design overhead. Moreover, the proposed methodology has very small workload and good migration ability. Finally, by full exploiting the fault tolerance property of CNNs, a highly reliable CNN accelerator with the proposed hybrid hardening strategy is implemented with Xilinx Zynq-7035. When BER is 2 × 10−6, the proposed hybrid hardening strategy reduces the whole system error rate by 78.95% with the overhead of an extra 20.7% of look-up tables (LUTs) and 20.9% of flip-flops (FFs).

A Radiation-Hardened Triple Modular Redundancy Design Based on Spin-Transfer Torque Magnetic Tunnel Junction Devices

Integrated circuits suffer severe deterioration due to single-event upsets (SEUs) in irradiated environments. Spin-transfer torque magnetic random-access memory (STT-MRAM) appears to be a promising candidate for next-generation memory as it shows promising properties, such as non-volatility, speed, and unlimited endurance. One of the important merits of STT-MRAM is its radiation hardness, thanks to its core component, a magnetic tunnel junction (MTJ), being capable of good function in an irradiated environment. This property makes MRAM attractive for space and nuclear technology applications. In this paper, a novel radiation-hardened triple modular redundancy (TMR) design for anti-radiation reinforcement is proposed based on the utilization of STT-MTJ devices. Simulation results demonstrate the radiation-hardened performance of the design. This shows improvements in the design’s robustness against ionizing radiation.

Построение эквивалентных схем в системах троирования

Triple-Modular Redundancy (TMR) technique is one of the widely used approaches to provide reliable functioning of logical circuits. In recent years, it has become possible to insert Trojan Circuits into the same line of each identical circuit of TMR, such an opportunity makes the TMR technique vulnerable. The way out of this situation is to use instead of three identical circuits either two approximate circuits or three equivalent circuits that differ in structural implementation from each other. The obtained equivalent circuits, in contrast to the use of approximating circuits, does not create an unprotected area in the TMR technique. An approach is proposed to obtain equivalent circuits based on distortion of the irredundant system of SoPs, which describes the behavior of the primary circuit of the TMR technique. The resulting distorted systems of SoPs and the original system of SoPs are used for the synthesis of circuits.

Estimation of the parameters of triple modular redundancy system under step partially accelerated life tests using Frechet distribution

Triple modular redundancy system (TMR) is repetition of important components or functions of the system. It aims to increase the reliability and reducing the failure rate. This study is focused on the estimating of the distribution’s parameters of the "TMR system" under the partly life test with gradual stress, as it included every component in the system that follows The Frechete distribution. This research aimed to analysis the reliability of this triple modular system. The optimal time for stress change was determined using two criteria according to the accelerated stress strategy under the new distribution, as well as estimating the reliability of the system by using the maximum likelihood (MLE) method. The efficiency of the " MLE" in estimate the parameters of the new distribution is one of the most important conclusions in this study. Therefore, the design of the "TMR” system can have a lengthy lifetime and higher safety, reducing the risks of unexpected failure and the economic losses.

Fault Identification in Modified Hybrid Digital Pulse Width Modulation using Triple Modular Redundancy

In this paper, the fault analysis is performed for the identification in the Modified Hybrid Digital Pulse Width Modulation by making use of the Triple Modular Redundancy method. The developed algorithm is real time implemented using the Xilinx Artix 7 FPGA device. The Modified Hybrid Digital Pulse Width Modulation is designed for the purpose of minimizing the Turn-ON and Turn-OFF delays in the triggering event of the generated Digital Pulse Width Modulation. Though additional compensatory circuits are added for the delay reduction, the area utilization is still low when implemented in FPGA device. Also, the Triple Modular Redundancy consists of three times of MHDPWM signal generation to check for the fault occurrence. For the sake of validating the fault identification, the majority voter circuit is used that could find the error at the earliest. The proposed method is checked for errors by inducing within the VHDL code and trailed with multiple duty cycle values. The proposed fault identification method is validated for VLSI parameters such as area, delay and power.

Performance Evaluation of Tilt-based Vehicle Accident Report System Using Triple Modular Redundancy

A vehicle accident report system was designed to detect accidents accurately and send message to related person. However, after accident, some components or modules can be damaged and it may cause failure of accident detection. Therefore, Triple Modular Redundancy (TMR) method was implemented in the system to mask faults within the modules and ensure the system to continue working. TMR is one of passive hardware redundancy methods. The system includes three MPU-6050 sensors functioning as vehicle tilt sensors to provide hardware redundancy, a TC9548A module serving as an I2C multiplexer, an Arduino Nano acting as a microcontroller and voter, and a NodeMCU ESP8266 responsible for transmitting message. Based on experiment results, the TMR system has a reliability value of 0.9928, a failure rate value of 0.0004/cycle, and accuracy of 3 sensor value of 85%. While, the non-redundancy system has a reliability value of 0.9286, a failure rate value of 0.0053/cycle, and accuracy of single sensor value of 57%. The results of the system process were sent to and displayed via an e-mail. It can be concluded that the TMR system has better performance than the non-redundancy one.

A 14T radiation hardened SRAM for space applications with high reliability

SummaryStatic Random Access Memory (SRAM) is vital in aerospace applications, but it may experience soft errors in strong radiation environments. This paper proposes a reconfigurable radiation SRAM with two operating modes catering to different environmental requirements: (1) traditional triple modular redundancy mode used when the radiation environment is strong and (2) SRAM cell expansion mode used when the radiation is not very strong. For example, when the memory capacity of a single module is 8 k, the memory capacity is 8 k in traditional triple modular redundancy mode, but it can be tripled to 24 K in extended mode. As can be obviously seen, this design can adjust the size according to the needs. In SRAM cell expansion mode, the proposed 14T SRAM cell enables the memory to maintain radiation resistance. Compared with DICE, RHBD‐12T, and WHIT, the read speed is improved by 3.8%, 5.7%, and 11.5% respectively, but compared with WE‐QUATRO, the read speed is reduced by 1.9%. The hold static noise margin is 1.378 times than DICE, 1.201 times than WE‐QUATRO, 1.045 times than RHBD‐12T, and 1.14 times than WHIT, respectively. The proposed 14T cell in this paper exhibits the highest critical charge value compared with the other cells. Combined with the expansion mode of the reconfiguration design, it shows great stability.

Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis

Hardware Trojans that have the capability to change the computed functional output in intellectual property (IP) cores, integrated into computing systems can be a vital reliability concern in the context of correct system operation. Therefore, determining an optimal Trojan-resistant hardware design architecture that considers multi-objective orthogonal parameters such as area and delay is crucial. This paper presents a novel exploration of optimal hardware IP core design methodology with Trojan defense capability (i.e., detection and isolation) during high level synthesis (HLS) that provides isolation of functional Trojan in a system design to ensure reliable and correct functional behavior. The proposed methodology is robust and provides the capability to yield the correct output value using HLS-based triple modular redundancy (TMR) logic and a distinct multivendor allocation policy. Therefore, the proposed HLS methodology can generate an optimal hardware IP core/system-on-chip (SoC) design with functional Trojan defense capability. The paper presents an overall flow of the proposed methodology along with a demonstrative case study on designing optimal Trojan resistant finite impulse response filter (FIR) hardware SoC design. Results of the proposed approach are evaluated in terms of design cost, convergence time, security and optimality analysis, and comparison with prior works. The proposed approach is able to generate fully functional Trojan-resistant optimal SoC designs with minimum overhead, as evident from optimality analysis and design cost.

RESAC: A redundancy strategy involving approximate computing for error-tolerant applications

Given the continuing miniaturization of underlying transistors, electronic functional units (circuits/systems) become increasingly susceptible to high-energy radiation, encountered in applications like space. Hence, redundancy is employed as a radiation hardening by design strategy to cope with faults of functional units used in such applications and to maintain their correct operation. Triple modular redundancy (TMR), which is a subset of N-modular redundancy (NMR), that can mask any single fault or a faulty functional unit has been widely used. However, compared to a simplex implementation a TMR implementation requires two additional functional units and a majority voting logic therefore a TMR implementation's area and power overheads are greater by over 200 %. This is burdensome for resource-constrained applications like space where low power and energy efficiency are important considerations. This paper presents a new redundancy strategy involving approximate computing called RESAC for error-tolerant applications such as digital image/video/audio processing, which is used in space systems. We evaluated the feasibility of RESAC for an image processing case study and the results confirm the usefulness. For implementation using a 28-nm CMOS technology, RESAC achieves reductions in area, delay, and power by 22.3 %, 15.3 %, and 24.9 % compared to TMR. Nonetheless, RESAC can address any NMR.

Advancements in Spaceborne Synthetic Aperture Radar Imaging with System-on-Chip Architecture and System Fault-Tolerant Technology

With the continuous development of satellite payload and system-on-chip (SoC) technology, spaceborne real-time synthetic aperture radar (SAR) imaging systems play a crucial role in various defense and civilian domains, including Earth remote sensing, military reconnaissance, disaster mitigation, and resource exploration. However, designing high-performance and high-reliability SAR imaging systems that operate in harsh environmental conditions while adhering to strict size, weight, and power consumption constraints remains a significant challenge. In this paper, we introduce a spaceborne SAR imaging chip based on a SoC architecture with system fault-tolerant technology. The fault-tolerant SAR SoC architecture has a CPU, interface subsystem, memory subsystem, data transit subsystem, and data processing subsystem. The data processing subsystem, which includes fast Fourier transform (FFT) modules, coordinated rotation digital computer (CORDIC) modules (for phase factor calculation), and complex multiplication modules, is the most critical component and can achieve various modes of SAR imaging. Through analyzing the computational requirements of various modes of SAR, we found that FFT accounted for over 50% of the total computational workload in SAR imaging processing, while the CORDIC modules for phase factor generation accounted for around 30%. Therefore, ensuring the fault tolerance of these two modules is crucial. To address this issue, we propose a word-length optimization redundancy (WLOR) method to make the fixed-point pipelined FFT processors in FFT modules fault tolerant. Additionally, we propose a fault-tolerant pipeline CORDIC architecture utilizing error correction code (ECC) and sum of squares (SOS) check. For other parts of the SoC architecture, we propose a generic partial triple modular redundancy (TMR) hardening method based on the HITS algorithm to improve fault tolerance. Finally, we developed a fully automated FPGA-based fault injection platform to test the design’s effectiveness by injecting errors at arbitrary locations. The simulation results demonstrate that the proposed methods significantly improved the chip’s fault tolerance, making the SAR imaging chip safer and more reliable. We also implemented a prototype measurement system with a chip-included board and demonstrated the proposed design’s performance on the Chinese Gaofen-3 strip-map continuous imaging system. The chip requires 9.2 s, 50.6 s, and 7.4 s for a strip-map with 16,384 × 16,384 granularity, multi-channel strip-map with 65,536 × 8192 granularity, and multi-channel scan mode with 32,768 × 4096 granularity, respectively, and the system hardware consumes 6.9 W of power to process the SAR raw data.

Cuckoo Bloom Hybrid Filter: Algorithm and Hardware Architecture for High Performance Satellite Internet Protocol Route Lookup

The next-generation satellite Internet Protocol (IP) router is required to achieve tens of millions of route lookups per second, since satellite Internet services based on low Earth orbit (LEO) constellations have become a reality. Due to the limitation of hardware resources on satellites and the high reliability requirements for equipment, a new satellite IP route lookup architecture is proposed in this paper. The proposed architecture uses a Bloom and cuckoo filter-based structure called cuckoo Bloom hybrid filter (CBHF), which guarantees only one off-chip memory access per lookup, to accelerate the Prefix-Route Trie (PR-Trie) algorithm. The proposed architecture has been evaluated through both a behavioral simulation in C++ language and a hardware implementation in Verilog hardware description language (HDL). Our simulation and implementation results show that the proposed satellite IP route lookup architecture can achieve a single-port throughput beyond 13 Gbps on a field programmable gate array (FPGA) board with a single DDR3 memory chip when operating at 200 MHz. In addition, the resource utilization in the FPGA shows that the proposed architecture also supports triple modular redundancy (TMR) to enhance reliability.