Triple Modular Redundancy Implementation Research Articles

RESAC: A redundancy strategy involving approximate computing for error-tolerant applications

Given the continuing miniaturization of underlying transistors, electronic functional units (circuits/systems) become increasingly susceptible to high-energy radiation, encountered in applications like space. Hence, redundancy is employed as a radiation hardening by design strategy to cope with faults of functional units used in such applications and to maintain their correct operation. Triple modular redundancy (TMR), which is a subset of N-modular redundancy (NMR), that can mask any single fault or a faulty functional unit has been widely used. However, compared to a simplex implementation a TMR implementation requires two additional functional units and a majority voting logic therefore a TMR implementation's area and power overheads are greater by over 200 %. This is burdensome for resource-constrained applications like space where low power and energy efficiency are important considerations. This paper presents a new redundancy strategy involving approximate computing called RESAC for error-tolerant applications such as digital image/video/audio processing, which is used in space systems. We evaluated the feasibility of RESAC for an image processing case study and the results confirm the usefulness. For implementation using a 28-nm CMOS technology, RESAC achieves reductions in area, delay, and power by 22.3 %, 15.3 %, and 24.9 % compared to TMR. Nonetheless, RESAC can address any NMR.

Analysis of Redundancy Techniques for Electronics Design—Case Study of Digital Image Processing

Electronic circuits/systems operating in harsh environments such as space are likely to experience faults or failures due to the impact of high-energy radiation. Given this, to overcome any faults or failures, redundancy is usually employed as a hardening-by-design approach. Moreover, low power and a small silicon footprint are also important considerations for space electronics since these translate into better energy efficiency, less system weight, and less cost. Therefore, the fault-tolerant design of electronic circuits and systems should go hand in hand with the optimization of design metrics, especially for resource-constrained electronics such as those used in space systems. A single circuit or system (also called a simplex implementation) is not fault-tolerant as it may become a single point of failure and is not used for a space application. As an alternative, a triple modular redundancy (TMR) implementation, which uses three identical copies of a circuit or system and a voter to perform majority voting of the circuits and systems outputs, may be used. However, in comparison with a simplex implementation, a TMR implementation consumes about 200% more area and dissipates 200% more power when circuits or systems are triplicated. To mitigate the area and power overheads of a TMR implementation compared to a simplex implementation, researchers have suggested alternative redundancy approaches such as selective TMR (STMR) insertion, partially approximate TMR (PATMR), fully approximate TMR (FATMR), and majority voting-based reduced precision redundancy (VRPR). Among these, VRPR appears to be promising, especially for inherently error-tolerant applications such as digital image/video/audio processing, which is relevant to space systems. However, the alternative redundancy approaches mentioned are unlikely to be suitable for the implementation of control logic. In this work, we analyze various redundancy approaches and evaluate the performance of TMR and VRPR for a digital image processing application. We provide MATLAB-based image processing results corresponding to TMR and VRPR and physical implementation results of functional units based on TMR and VRPR using a 28-nm CMOS technology.

Area, Power and Speed Optimized Early Output Majority Voter for Asynchronous TMR Implementation

This paper presents a new, efficient asynchronous early output majority voter that can be used to effectively realize an asynchronous triple modular redundancy (TMR) implementation. For the input-output mode asynchronous realization, the dual-rail code was used for data encoding and four phase return-to-zero and return-to-one handshake schemes were separately used for data communication. The proposed majority voter requires 62.8% less area and dissipates 37% less power on average compared to the best of the existing asynchronous majority voters while considering both handshake schemes. Importantly, the reductions in area and power are achieved without sacrificing the speed. Example TMR implementations show that the proposed majority voter leads to simultaneous reductions in cycle time, silicon area, and power dissipation. As a result, the proposed majority voter enables improved optimization in figure-of-merits such as area–cycle time product, power–cycle time product, and area–cycle time–power product for TMR implementations utilizing it compared to TMR implementations incorporating other majority voters. The circuits were implemented using a 32/28-nm CMOS technology.

Quasi Delay Insensitive Majority Voters for Triple Modular Redundancy Applications

Mission- and safety-critical applications tend to incorporate triple modular redundancy (TMR) in their hardware implementation to reliably withstand the fault or failure of any one of the function modules during normal operation, and the function module may be a circuit or a system. In a TMR implementation, two identical copies of a function module are used in addition to the original function module, and the correct operation of at least two function modules is required. In TMR, the corresponding primary outputs of the three function modules are combined using majority voters, which determine the actual primary outputs based on the Boolean majority. Hence, the majority voter is an important component that is useful for conveying the correct operation of a TMR implementation. In the existing literature, many designs of three-input majority voters for TMR have been discussed. However, most of these correspond to the synchronous design style and just one corresponds to the bundled-data asynchronous design style, which is not delay insensitive and hence non-robust. To our knowledge, a robust delay insensitive design of the three-input majority voter has not been considered. In this context, this article presents the designs of robust quasi delay insensitive (QDI) three-input majority voters based on QDI logic synthesis methods, and analyzes which majority voters are preferable in terms of speed, power, and area. We implement example QDI TMR circuits using a QDI full adder as the function module and QDI majority voters using 32/28 nm complementary metal oxide semiconductor (CMOS) technology. The QDI TMR implementations use the delay insensitive dual rail code for data encoding, and four-phase return-to-zero and four-phase return-to-one handshake protocols for data communication.

Reliability Calculation With Respect to Functional Failures Induced by Radiation in TMR Arm Cortex-M0 Soft-Core Embedded Into SRAM-Based FPGA

This paper presents comparative results from fault injection (FI) and heavy ions accelerated irradiation on a Xilinx 7 series static RAM (SRAM)-based field-programmable gate array (FPGA) for a soft-core microprocessor mitigated by triple modular redundancy (TMR) with different levels of granularity. The Arm Cortex-M0 soft-core processor executing two software applications is employed as a case study. The TMR implementation is automatically generated from synthesized netlist and includes coarse and fine grain variants. Apart from the TMR mitigation, the configuration memory scrubbing is used as implemented by the engine natively available on Xilinx 7 series FPGAs. Experiments with FI and heavy ions allow analyzing the effectiveness of the automated TMR mitigation combined with memory scrubbing and also to analyze the consistency of reliability metrics from FI and heavy ions. The dynamic cross section of the design was improved up to 4.5 times according to the implemented TMR granularity and when associated with the configuration memory scrubbing.

An Efficient Technique to Protect Serial Shift Registers Against Soft Errors

This brief presents a technique to efficiently correct single soft errors in serial shift registers. The proposed scheme uses two copies of the shift register. To achieve error correction, data are convolutionally encoded at the input of one of the copies and are decoded at its output. This processing ensures that in that copy, any error affecting a single bit will corrupt its output for multiple cycles. On the other hand, a single-bit error in the original copy will corrupt its output only for one cycle. Therefore, the error patterns can be used to identify the copy that has suffered the error and, consequently, to correct the error. The proposed technique has been implemented in a Hardware Description Language and implemented in a 45-nm library. A fault injection tool has been used to evaluate the effectiveness of the proposed scheme, showing that it can correct all single soft errors. The cost of the proposed approach in terms of circuit area has been compared with a traditional triple-modular redundancy implementation. The results show significant cost reductions, which approach a factor of 33% for large shift registers.

Single event upset mitigation techniques for FPGAs utilized in nuclear power plant digital instrumentation and control

Field programmable gate arrays (FPGAs) are integrated circuits being increasingly used for digital instrumentation and control (I&C) in nuclear power plants (NPPs) because of low cost, re-configurability and low design turn-around time. However, to ensure reliability, proper design techniques must be employed since the memory and logic in FPGAs are susceptible to single event upsets (SEUs). Triple modular redundancy (TMR) has become a common SEU mitigation design technique because of its straightforward implementation and reliable results. Partitioned TMR approaches are introduced in this paper, and formulae derived indicate that the maximum probability of two simultaneous errors [ P E] max is inversely proportional to the number of logic partitions in a TMR design, when each redundant logic block in every logic partition has the same number of sensitive nodes. However, the maximum logic partitioning design cannot completely eliminate the possibility of two simultaneous upsets. For the example test circuit it is found that [ P E] max is reduced dramatically from 66.67% for minimum logic partitioning to 4.44% for maximum logic partitioning. Because TMR introduces significant overhead due to its full hardware redundancy, a dual modular redundancy approach is also examined for application to less demanding situations. By comparative analysis this study reaches the conclusion that the maximum logic partitioning TMR implementation is the best solution for digital I&C applications in NPPs where obtaining robustness is of the highest importance, despite its higher area overhead.

Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits

Due to the shrinking of feature size and significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, interference from radiation and noise-related transient faults. Many of these faults are not permanent in nature but their occurrence can result in malfunctioning of circuits, either due to complexity of digital circuits or due to interaction with software. A fault-tolerant scheme such as triple-modular redundancy (TMR) is being implemented increasingly in digital systems. One of the drawbacks of this scheme is that the reliability of the voter circuit is assumed to be very high, which may not be true. Most of the implementation of digital circuits is in the form of integrated circuit; so all the circuit elements are fabricated with same technology and hence reliability of all the components is usually same. In this paper we are presenting a novel fault-tolerant voter circuit which itself can tolerate a fault and give error free output by improving the overall system’s reliability.

Fault-Tolerant ICs: The Reliability of TMR Yield-Enhanced ICs

The use of triple modular redundancy (TMR) for reliability enhancement is well known. This paper presents a simple method' for predicting the reliability of integrated circuits (ICs) which use TMR for yield enhancement. A simple yield-model is included as it is necessary to factor in the effect of consumption of redundancy paths due to wafer fabrication defects. TMR implementation is briefly discussed as well.