Triple Layer Metal Research Articles

Prompt-gamma activation analysis and neutron imaging of layered metal structures

We present here Monte Carlo computer simulations to broaden the scope of the prompt-gamma activation analysis (PGAA) from the elemental composition measurement of ideal, point-like, homogeneous samples towards non-homogeneous or heterogeneous but still regularly-shaped samples. The successful correction for the negative matrix effect related to the neutron self-shielding and gamma self-absorption is a key step in the quantitative analysis of layered metal structures. This geometry is relevant to practical cases where corrosion layer, patina, paint, coating, gilding, or segregation are present on the surface of a core metal. Linear neutron attenuation coefficients are measured in a polychromatic neutron beam by radiography, while the gamma attenuation calculations by MCNP6 simulations were validated by gamma transmission measurements. Finally, the method was successfully applied to correct for the PGAA matrix effect in double- and triple-layer metal stacks and a real structured numismatic sample.

A Novel approach to fabricate self‐aligned graphene transistor

An innovated simple fabrication process is adopted to fabricate a novel gate self-aligned (GSA) graphene field effect transistor (GFET). First, stacked source/drain electrodes with triple-layer metal are formed. Then, after slightly etching of the second metal layer, laterally recessed profiles are formed, which leads to the self-aligned (SA) gate. A noticeable feature of the GSA-GFET is that the access resistance is not changed with the level of the lateral recessing, which leads to a very small access resistance. Compared with the non-SA-GFET with same gate length and width, the contact resistance of the GSA-GFET is reduced by 68%, the peak gm is 3.6 times improved, the on/off ratio is increased from 1.8 to 3.2.

A fast-response/recovery ZnO hierarchical nanostructure based gas sensor with ultra-high room-temperature output response

In this paper, a ZnO hierarchical nanostructure based gas sensor is presented. The proposed implementation features short response/recovery time and ultra-high output response at room temperature (RT). In order to take the advantages of complementary-metal-oxide-semiconductor (CMOS) process in terms of miniaturization and cost-effectiveness, a novel fabrication recipe, consisting of CMOS-compatible techniques, is proposed to form a patterned triple-layer metal, which functions as both interconnection electrodes and catalyst for our reported ZnO hierarchical nanostructure. This enables rapid and local growth of ZnO hierarchical nanostructure directly on a single silicon chip. Reported peak RT output response of 32 (20ppm NO2) provides a significant 28-fold improvement over the traditional widely adopted nanowire-based gas sensor. Meanwhile, a time efficient gas sensor is also validated by the presented temporal performance with a response and recovery time of 72s and 69s, respectively. In addition, compared with the previously demonstrated gas sensors operating at 200–300°C, the proposed RT sensing completely removes the power-hungry heater and eliminates the related thermal reliability issues. Moreover, the demonstrated process flow well addresses the challenging issues of the traditional mainstream “drop-cast” method, including poor yield, non-uniformity of device performance and low efficiency caused by inevitable manual microscope inspection.

Management of malignant gastric outlet obstruction with a modified triple-layer covered metal stent

A high incidence of migration with covered metal stents has been reported in malignant gastric outlet obstruction (GOO). A newly modified, partially covered, triple-layer nitinol stent was developed that has a longer uncovered portion (5-15 mm) to prevent stent migration. To estimate the efficacy and safety of the modified covered, triple-layer metal stent. Multicenter, prospective cohort study. Three tertiary referral centers. Fifty consecutive patients (26 with pancreatic carcinoma, 14 with gastric carcinoma, 9 with cholangiocarcinoma, 1 with a metastatic node) who presented with symptomatic unresectable malignant GOO between April 2007 and March 2010. Endoscopic placement of the modified covered, triple-layer metal stent. The primary endpoint was to improve the GOO scoring system (GOOSS) score. Secondary endpoints were success rate, patency, and complications. The median GOOSS score improved significantly (P < .0001) after stenting (from 0 to 3). The technical and clinical success rates were 100% and 90%, respectively. Stent occlusion by tumor overgrowth or ingrowth at the uncovered portion developed in 5 patients (10%). Asymptomatic stent migration occurred in 3 patients (6%) receiving chemotherapy at 95, 230, and 553 days after stent placement, but these patients tolerated solid food 68, 260, and 142 days after stent migration, respectively. Other complications occurred in 1 patient with insufficient expansion, cholangitis, and pancreatitis. No procedure-related deaths occurred. A single-arm study in tertiary-care centers. The modified covered, triple-layer metal stent was effective and safe for managing malignant GOO and can prevent tumor ingrowth and stent migration. ( UMIN000004566.).

Fabrication of Robust Triple- Ti1 − xAlxN Metal Gate by Atomic Layer Deposition

In this study, we fabricate a thermally stable triple- metal gate for potential use in p-type metal-oxide-semiconductor devices and analyze the impact of Al concentrations in an atomic-layer-deposited film on the effective work function and the resistivity of the metal gate. An increase in the Al content in the film causes an increase in the resistivity of the film metal gate while improving the thermal stability of the metal gate. By combining the positive effects in terms of the work function and the resistivity, we prepared a triple-layer metal gate, which exhibits a work function of and resistivity of after thermal annealing at in for , making it suitable for use as a metal gate in pMOS field-effect transistors.

An Efficient Hardware Architecture of Intra Prediction and TQ/IQIT Module for H.264 Encoder

In this paper, we propose a novel hardware architecture for an intra-prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing 4×4 Hadamard transform and quantization during 16×16 prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix 0.35 µm TLM (triple layer metal) library.

MDSP-II: a 16-bit DSP with mobile communication accelerator

This paper describes a 16-bit programmable fixed-point digital signal processor, called MDSP-II, for mobile communication applications. The instruction set of MDSP-II was determined after a careful analysis of the Global System for Mobile communications (GSM) baseband functions. An application-specific hardware block called the mobile communication accelerator (MCA) was incorporated on chip to accelerate the execution of the key operations frequently appearing in Viterbi equalization. With the assistance of MCA, the GSM baseband functions, which need 53 million instructions per second (MIPS) on the general-purpose digital signal processors, can be performed only with 19 MIPS. The MDSP-II was implemented with a 0.6-/spl mu/m triple-layer metal CMOS process on a 9.7/spl times/9.8 mm/sup 2/ silicon area and was operated up to 50 MHz clock frequency.

An efficient frame memory interface of MPEG-2 video encoder ASIC chip

This paper presents an efficient frame memory interface of MPEG-2 video encoder which is accomplished in not only reducing interface buffer size through efficient memory map organization and access timing schedules but also avoiding unnecessary small size buffers and simplifying their control circuits. In this design, 0.5 /spl mu/m CMOS TLM (triple layer metal) standard cells are used as design libraries, and VHDL simulator and logic synthesis tools are used for hardware design and verification, and the hardware emulator that is a C-language model of the proposed architecture is exploited for various test vector generation and functional verification. The improved frame memory interface module takes about 58% less hardware area than the previous design (Kim et al. 1997), and results in reducing the total hardware area of the video encoder ASIC chip up to 24.3%. We also reduced the random memory accesses to save the power consumption caused by the transition of the system-level I/O buses.

A block processing unit in a single-chip MPEG-2 video encoder LSI

This paper describes a block processing unit in a single-chip MPEG-2 MP@ML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 /spl mu/m triple-layer metal CMOS cell-base technology at 54 MHz.