Trigger Subsystems Research Articles

Hardware design and testing of the generic rear transition module for the global trigger subsystem of ATLAS Phase-II Upgrade

In the framework of the ATLAS experiment’s Phase-II Upgrade at the High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 μs-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. The implementation of the functionality is firmware-focused and composed of several processing nodes, which are hosted on identical hardware, made up of an Advanced Telecommunications Computing Architecture (ATCA) front board, called Global Common Module (GCM), and a rear transition module (RTM), called Generic RTM (GRM). The GRM, which was developed to mitigate the risks deriving from the complex design and power management of the GCM, features an advanced Xilinx Versal Prime system-on-chip and can handle communication with the GCM and Front-End Link eXchange (FELIX) subsystem and trigger processors through 124 25.8 Gb/s transceiver links, for readout and control. Additionally, the GRM mounts a Low-Power GigaBit Transceiver (lpGBT) chip which enables emulation of the detector front-ends for integration tests. This paper presents the GRM hardware design and its testing.

Prototype hardware design and testing of the global common module for the global trigger subsystem of the ATLAS phase-II upgrade

The High-Luminosity Large Hadron Collider (HL-LHC) will deliver more than ten times the integrated luminosity of the previous runs combined. Meeting its stricter throughput requirements poses new challenges to the Trigger and Data Acquisition (TDAQ) systems of the LHC experiments. Introduced in the framework of the ATLAS experiment’s HL upgrade, the Global Trigger (GT) is a new subsystem which will perform offline-like algorithms on full-granularity calorimeter data. The implementation of the GT’s functionality is firmware-focused and is composed of three layers: multiplexing (or data aggregating), global event processing, and demultiplexing interface to the central trigger processor. Each layer will be composed of several, similar nodes, hosted on replicas of identical hardware, the Global Common Module (GCM), an ATCA front board which is designed to be adopted throughout the entire GT subsystem. This article proceeds from the TWEPP 2021 conference and presents the GCM hardware design, performed in 2020, and focuses on some key results of its extensive testing performed in 2021.

Multiplexing Firmware Prototypes for the Global Trigger Subsystem of ATLAS Phase-II Upgrade

As part of the ATLAS experiment's Phase-II Upgrade, improved trigger hardware and algorithms will be implemented onto a single-level architecture. The global trigger (GT) subsystem is a new firmware (FW)-focused project designed to meet stringent requirements from the high-luminosity runs of the large hadron collider (LHC). The global multiplexer (MUX) is the input aggregating stage of the GT; it performs three main tasks: 1) aggregating data from several sources, connected with more than 2300 input fibers, under different protocols; 2) time-multiplexing the incoming data, to sort the packets per bunch-crossing (BC) events, by compensating the relative skews across the various serial input channels; and 3) transmitting, in a round-robin fashion, the sorted BC data to the global event processor (GEP) array, which is the following stage of the GT subsystem and is composed of 48 nodes, each one processing a single BC event. Two MUX FW prototypes for the Global Feature EXtractor (gFEX, part of the liquid argon calorimeter trigger) inputs have been designed, implemented, and validated on a gFEX production board, for up to 72 input and output channels. A four-channel version has been completed with I/O interfaces and validated in a full-chain design, accepting 8b/10b encoded inputs at 11.2 Gb/s and transmitting at 25.78125 Gb/s under Xilinx Aurora 64b/66b protocol. The total latency has been benchmarked in all of its contributing subcomponents and proven to meet the requirements from the Technical Design Report for the Phase-II Upgrade of the trigger and data acquisition system.

Upgrade of the CMS Global Muon Trigger

The increase in center-of-mass energy and luminosity for Run-II of the Large Hadron Collider poses new challenges for the trigger systems of the experiments. To keep triggering with a similar performance as in Run-I, the CMS muon trigger is currently being upgraded. The new algorithms will provide higher resolution, especially for the muon transverse momentum and will make use of isolation criteria that combine calorimeter with muon information already in the level-1 trigger. The demands of the new algorithms can only be met by upgrading the level-1 trigger system to new powerful FPGAs with high bandwidth I/O. The processing boards will be based on the new μTCA standard. We report on the planned algorithms for the upgraded Global Muon Trigger (μGMT) which sorts and removes duplicates from boundaries of the muon trigger sub-systems. Furthermore, it determines how isolated the muon candidates are based on calorimetric energy deposits. The μGMT will be implemented using a processing board that features a large Xilinx Virtex 7 FPGA. Up to 72 optical links at 10 Gb/s will be used to receive muon candidates and energy sums from the calorimeter trigger. Muon candidates will be received directly from the sector processors of the upgraded trigger, absorbing the final sorting stage of each muon sub-system and thus minimizing the latency of the trigger.

Upgrade of the trigger system of CMS

Various parts of the CMS trigger and in particular the Level-1 hardware trigger will be upgraded to cope with increasing luminosity, using more selective trigger conditions at Level 1 and improving the reliability of the system. Many trigger subsystems use FPGAs (Field Programmable Gate Arrays) in the electronics and will benefit from developments in this technology, allowing us to place much more logic into a single FPGA chip, thus reducing the number of chips, electronic boards and interconnections and in this way improving reliability. A number of subsystems plan to switch from the old VME bus to the new microTCA crate standard. Using similar approaches, identical modules and common software wherever possible will reduce costs and manpower requirements and improve the serviceability of the whole trigger system. The computer-farm based High-Level Trigger will not only be extended by using increasing numbers of more powerful PCs but there are also concepts for making it more robust and the software easier to maintain, which will result in better efficiency of the whole system.

BES III TOF Trigger Sub-System

The time-of-flight (TOF) is one of the Beijing Spectrometer III (BES III) subsystems. Its trigger logic is implemented on a 9U VME board equipped with a rear side plug-in transition module. This trigger logic makes prompt decisions to select interesting physics events. These decisions are made by evaluating the relevant hit information from the 272 scintillators that compose the TOF detector. The accessory VME transition modules, which are plugged into the rear of the TOF readout electronics VME crate, transfer the 272 hit signals into the trigger module. A total of 34 fiber optical links are allocated to bring the raw hit information from the TOF readout electronics to the trigger module. In practice, only 28 fiber-optical links have been used. According to the physics requirements, the TOF trigger module generates 7-bit real-time trigger signals that are passed to the global trigger system, where the primary L1 trigger decision is made. In addition, the TOF trigger subsystem also sends 136-bit position-hit data to the Track-Match-Logic modules in the global trigger system for particle track processing in real time. The trigger logic algorithms are implemented in nine Altera EP1K30 and one EP1S40 field-programmable gate array (FPGAs) in the TOF trigger module. Compared to the previous Beijing Spectrometer TOF trigger subsystem, the employment of high-capacity FPGAs in the trigger module has the advantage of reconfiguration if the physics requirements evolve in the future. During the tests carried out after the assembly of the entire BES III system, the TOF trigger subsystem performed reliably and efficiently.

High-speed electronics of the T0 detector for the ALICE experiment (CERN)

The design and special features of the main units of high-speed electronics for the trigger subsystem of the T0 detector of the ALICE experiment are considered. Its characteristic time resolution is 50 ps. The dead time does not exceed 25 ns.

Conceptual design of the CMS trigger supervisor

The Trigger Supervisor is an online software system designed for the CMS experiment at CERN. Its purpose is to provide a framework to set up, test, operate and monitor the trigger components on one hand and to manage their interplay and the information exchange with the run control part of the data acquisition system on the other. The Trigger Supervisor is conceived to provide a simple and homogeneous client interface to the online software infrastructure of the trigger subsystems. The functional and nonfunctional requirements, the design, the operational details, and the components needed in order to facilitate a smooth integration of the trigger software in the context of CMS are described.

A first level trigger subsystem CIP2k for the H1 experiment at HERA

The ep-collider HERA at DESY and the high energy physics experiment H1 were upgraded in the years 2000–2002. A specific luminosity three times higher than before has recently been observed. To cope with the higher luminosity and the more complex background situation a set of five new cylindrical multiwire proportional chambers (CIP2k) were built providing information to distinguish between beam-gas induced background events and true ep-interactions within 2.3 microseconds on a first level trigger stage using all channels of the chambers. The five cylindrical chambers with a cathode pad readout have each a 16 fold segmentation of the azimuth angle and a segmentation of about 120 in z along the beam axis. The total number of readout channels amounts to 9600. Groups of 60 cathode pads are read out via striplines by a custom designed readout chip (CIPix). The on-chamber electronics digitizes and multiplexes the data and sends it via optical links to the trigger and data acquisition system at a rate of about 10 GBit/s per optical link. A histogram of the vertex distribution along the beam axis of the tracks crossing the chamber is calculated by the trigger system. From this histogram trigger informations are derived dividing the histogram in regions of background and physics events. The tracking algorithm is based on bit pattern comparison of pad data. Field-programmable gate arrays (FPGA) were chosen to accomplish this complex and highly parallelized task. In addition the FPGAs contain pipelines to store the chamber data making it possible to read out the information if a trigger occurs. The trigger, data acquisition and high voltage system are controlled and monitored by the experiment control system (ECS) based on commercial software called PVSSII.

The CDF and DØ Upgrades for Run II

▪ Abstract The DØ and CDF collaborations are preparing their detectors for the Tevatron Run II. A 20-fold increase in integrated luminosity is planned for the first two years of the upcoming run, and the detector subsystems are undergoing substantial improvements to handle the higher rates as well as to better measure the products of the [Formula: see text], interactions. This review discusses the physics goals that motivate these detector enhancements and describes in detail the improvements being made to the charged particle tracking, calorimetry, muon identification, and trigger subsystems of both detectors.

Using modern software tools to design, simulate and test a Level 1 trigger sub-system for the D Zero detector

The work presents a system which uses a commercial spreadsheet program and commercial hardware on an IBM PC to develop and test a track finding system for the D Zero Level 1 scintillating fiber trigger. The trigger system resides in a VME crate. This system allows the user to generate test input, write the pattern to the hardware, simulate the results in software, read the hardware result, compare the results and inform the user of any differences.

DIII-D Timing System

The DIII-D tokamak, an upgrade of Doublet III, a device to study magnetic confinement fusion at GA Technologies, became operational in February 1986. The new timing system consists of two major subsystems. The trigger subsystem synchronizes control and data acquisition for the experiment. The clock subsystem is a centralized source of pulses for data acquisition equipment. The CAMAC hardware and the database software for the DIII-D timing system is discussed.