Trench Refill Research Articles

Epitaxial trench refill of 4H-SiC by chlorinated chemistry

Trench epitaxy of 4H-SiC is investigated with the supersaturation of chlorinated chemistry at a growth temperature of 1550 °C. Coupled with a lower growth temperature than has been previously reported, the integrity of the 4H-SiC trenches is retained and minimal rounding effects of H2 annealing prior to growth are observed. The system gives different growth rates of materials on the various crystal faces of the trenches and can be used to improve the refilling process, resulting in the reduced void formation. The addition of excessive levels of HCl can suppress trench epitaxy by reducing the growth rate on the sidewalls of trenches in favor of growth on the surface. The processes demonstrated offer a scalable and reproducible method to fabricate SiC-based superjunction device structures for applications in high voltage power electronics.

Monolithic SOI through-wafer Knudsen pumps with mechanically robust Si channels

Knudsen pumps (KPs) generate gas flow using thermal transpiration in narrow channels with a longitudinal temperature gradient. With no moving parts, KPs offer long lifetime and are attractive for complex microfluidic systems. Although high performance was previously reported in microfabricated KPs that utilized suspended dielectric membranes to construct the pumping channels, this approach can limit the mechanical robustness and complicate the fabrication process. In this work, we present monolithically microfabricated KPs without using suspended membranes. These types of structures significantly improve the mechanical robustness, allow a wider process window, and simplify the microfabrication process. The pumping channels in this work are 14 µm in length, 1.2 × 200 µm2 in cross-section, vertically oriented, and with rigid silicon and dielectric sidewalls; the overall structures are easily manufacturable. This work primarily focuses on two core KP designs, which incorporate 4 and 6 parallel pumping channels in ≈ 11 and 17 mm2 footprints, respectively. The scaling capability is also investigated preliminarily in a design with 45 parallel pumping channels. The KPs were fabricated on a silicon-on-insulator wafer by a six-mask lithographic process with standard fabrication steps. This process eliminated the use of complicated trench refill, polish, and sacrificial dry etch steps that were required for the previously reported KPs with suspended membranes. At atmospheric pressure, the 4-channel KPs provided a blocking pressure of 620 Pa and maximum flow rate of 0.041 sccm through 0.001 mm2 channel area, using 2 W applied power. This maximum flow rate per unit channel area (sccm/mm2) is superior to that of the KPs with suspended membranes. For all the KP designs, the experimentally measured pumping performance well matched the modeling results, with <15 % discrepancy. The fabrication simplicity and reliability of the mechanically robust KPs can enable monolithic integration onto complex lab-on-a-chip systems.

Method for Keyhole-Free High-Aspect-Ratio Trench Refill by LPCVD.

In micro-machined micro-electromechanical systems (MEMS), refilled high-aspect-ratio trench structures are used for different applications. However, these trenches often show keyholes, which have an impact on the performance of the devices. In this paper, explanations are given on keyhole formation, and a method is presented for etching positively-tapered high-aspect ratio trenches with an optimised trench entrance to prevent keyhole formation. The trench etch is performed by a two-step Bosch-based process, in which the cycle time, platen power, and process pressure during the etch step of the Bosch cycle are studied to adjust the dimensions of the scallops and their location in the trench sidewall, which control the taper of the trench sidewall. It is demonstrated that the amount of chemical flux, being adjusted by the cycle time of the etch step in the Bosch cycle, relates the scallop height to the sidewall profile angle. The required positive tapering of 88° to 89° for a keyhole-free structure after a trench refill by low-pressure chemical vapour deposition is achieved by lowering the time of the etch step.

(Invited) Medium-Voltage SiC Devices for Next Generation of Power Conversion

As a wide bandgap semiconductor, Silicon Carbide (SiC) power switches and diodes offer the promise of lower conduction and switching losses and more efficient power conversion for a wide range of applications that include but not limited to hybrid vehicles, renewable technologies, industrial motors and data centers. However, in present day, SiC solutions for MV-class (>3.3 kV) unipolar switches and diodes suffer from high conduction losses at elevated temperatures, and SiC bipolar devices such as IGBTs require a prohibitive high forward voltage drop of 3V. Therefore, in these systems, the advantage of SiC technology is diminished compared to the incumbent Si IGBT technology. SiC super-junctions (SJ) can break the unipolar limit and offer an improved trade-off between specific on-resistance and blocking voltage for MV-class applications. To date, multi-epitaxial growth and trench-refill approaches have been demonstrated for 1.2kV and 6.5kV SiC SJ devices. Due to low diffusivity of dopants and shallow projectile depth of implanted atoms in SiC, multi-epitaxial solutions are limited to low voltage switches with thinner drift layers (up to 1200V). Alternately, the trench refill approach generates crystallographic defects that result in leakage at high blocking voltages. Furthermore, achieving uniform, target dopant distribution inside re-grown layers requires complex growth conditions and makes the regrowth process challenging. Recently, SiC charge-balanced (CB) diodes and MOSFETs were reported as an alternative solution to SJ devices with a simpler and scalable fabrication process. In these devices, a novel drift layer architecture is implemented with buried p-doped regions inside the drift layers instead of p-doped pillars. This new approach has been adopted for 3.3kV SiC JBS diodes and 4.5kV SiC MOSFET and results in Ron,sp significantly below the 1-D SiC unipolar limit. In the meantime, a new class of SJ devices is being developed that relies on Megavolt-level implantation to form deep p-type and n-type pillars. This multi-epitaxial SJ approach can be implemented in high voltage SiC devices with a smaller number of regrowth steps. In this work, we review fabrication steps for realizing SiC CB diodes and MOSFETs and report static characterization from room temperature up to 175 °C and dynamic response up to 3kV double pulse switching of such diodes and MOSFETs. Furthermore, we report successful fabrication of 2kV SiC SJ PiN diodes as a first building block of deep-implanted SJ technology and will discuss effect of different activation anneal temperatures on recovering lattice damage following high energy implantation.

An All-Silicon Process Platform for Wafer-Level Vacuum Packaged MEMS Devices

Thispaper introduces a novel, inherently simple, and all-silicon wafer-level fabrication and hermetic packaging method developed for MEMS devices. The proposed method uses two separate SOI wafers to form highly-doped through-silicon vias (TSVs) and suspended MEMS structures, respectively. These SOI wafers are then bonded by Au-Si eutectic bonding at 400 °C, achieving hermetic sealing and signal transfer without requiring any complex via or trench refill process steps. The package vacuum is measured using encapsulated MEMS resonators to be as low as 15 mTorr with the help of successfully activated thin-film getters. The combined fabrication and packaging yield is around %89 and chips still maintain a package pressure below 100 mTorr after more than 6 years. The packages show an extremely high strong bonding strength (>40 MPa) and are proved to remain hermetic after temperature cycling (25 °C-85 °C) and harsh temperature shock (5 min@300 °C) tests. The all-silicon MEMS resonators fabricated and packaged using the proposed method project up to a 2.3× enhancement in the bias instability and ~ 4× in the temperature sensitivity of frequency output compared to an identical MEMS resonator fabricated using the silicon-on-glass (SOG) technology.

Modeling and Analysis of 3-D Core-Shell Superjunction Structures

Conventional superjunction (SJ) structures are composed of p- and n-type doped pillars extending longitudinally as linear stripes (LSs). The reduced surface field (RESURF) effect in these structures is essentially due to a 2-D depletion. A 3-D RESURF is expected to be better than a 2-D RESURF and may further improve the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {BV}-\text {R}_{\text {DS}{(} \text {on} {)},\text {sp}}$ </tex-math></inline-formula> tradeoff for SJ devices. A natural 3-D RESURF structure is a core-shell (CS) SJ structure with a cylindrical unit cell. To identify and leverage the advantages that a 3-D RESURF can offer, the CS SJ is theoretically and numerically analyzed in this article. We develop an analytical model that results in closed-form expressions for the electric field profiles in both CS and LS structures. A very close agreement is observed between the analytical results and numerical simulations. The efficacy of 2-D and 3-D RESURF is compared using the model, and it is found that neither of these designs is universally better. The superior design is determined by the fabrication technology limitations. For trench refill type technologies, the CS design can offer substantial improvement, but, for lithography limited technologies, the CS design shows a significant deterioration in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {BV}-\text {R}_{\text {DS}{(} \text {on} {)},\text {sp}} $ </tex-math></inline-formula> tradeoff compared with the LS design.

Self‐Align Fabrication of Narrow‐Gapped Dual AFM Tip Using Si Trench Refilling with SOG and Magnetostrictive Film Stacked Dual Cantilever Formation

SUMMARYThis paper reports on a novel self‐align fabrication process of narrow‐gapped dual AFM (atomic force microscope) tip. The dual AFM tip was fabricated on (100) orientated Si substrate by using narrow trench etching, trench refilling with SOG (spin‐on‐glass), CMP (chemical–mechanical polishing), and Si crystalline anisotropic etching. Through the process, a sharp dual AFM tip with a gap of 500 nm, which was defined only by the etched trench width, was successfully fabricated. Although another fabrication process using an acrylic‐nitrile‐styrene‐epoxy resin refilling was also attempted, a dual tip was not obtained due to the poor adhesion of the resin in the silicon etching process. In addition, a dual AFM cantilever (magnetostrictive film/Si 2.0 μm) was formed by MEMS fabrication. The fabricated FePd 0.4 μm/Si 2.0 μm and Ni 1.3 μm/Si 2.0 μm cantilever were individually deflected to 1.4 μm at 300 Gauss and 0.4 μm at 240 Gauss due to effects of magnetic flux and negative magnetostriction, respectively.

A CMOS compatible process for monolithic integration of high-aspect-ratio bulk silicon microstructures

We report a CMOS compatible bulk micromachining method for the integration of high-aspect- ratio single crystal silicon MEMS (micro electromechanical systems) devices and signal conditioning circuit on a standard silicon wafer. The trench refilling and residual silicon removing techniques are used to acquire a proper electrical insulation between the different actuation and sensing elements situated on either fixed or movable parts of an MEMS device. To demonstrate the compatibility of the process, an integrated MEMS accelerometer was implemented. Test results show that the resistance between different elements of the device is larger than 10 12 Ω. The electrical properties of the transistors that experienced MEMS fabrication agree well with those without MEMS process, indicting the CMOS compatibility of the process.

A Novel Fabrication Method for Flexible SOI Substrate Based on Trench Refilling with Polydimethylsiloxane

Flexible arrays based on the flexible connection of double layers are demonstrated. Flexible sensor arrays are highly desired for many applications. Conventional flexible electronics are implemented by directly fabricating them on organic flexible substrates such as polyimide or polyethylene terephthalate, or forming on rigid substrates and then transferring them onto elastomeric substrates. For the first time, a novel process method based on trench refilling with polydimethylsiloxane to make flexible arrays is proposed. In this method, the sensors are directly fabricated on islands of the final bulk silicon. The performance of the sensor will not to be effected by bending and stretching operations. A one-dimensional flexible array shows good flexibility. Since the flexibility process is the last fabrication step, this method is compatible with many micro-electro-mechanical system fabrication technologies and has good yield.

Highly Reproducible Nanolithography by Dynamic Plough of an Atomic-Force Microscope Tip and Thermal-Annealing Treatment

An approach has been developed to use atomic-force microscope (AFM) to pattern materials at the nanoscale in a controlled manner. By introducing a thermal-annealing process above the glass-transition temperature of poly (methylmethacrylate) (PMMA), the profile of indented nanopatterns has been dramatically improved by abatement of the tip-induced debris. This eliminates the main problem of the previous AFM-based tip-ploughing lithography method, namely the debris formation during the nanoplough and trench refilling by debris. We are able to reproducibly fabricate nanopatterns down to 40 nm. Meanwhile, the AFM-tip lifetime has been increased substantially. In particular, the adhesion between the PMMA layer on the edge of trenches and the substrate is significantly improved to enable reliable pattern transfer into GaAs/AlGaAs heterostructures by wet-chemical etching. Functional nanodevices with a lateral feature size of 100 nm to an etching depth of 70 nm are demonstrated using the method.

An In-Plane High-Sensitivity, Low-Noise Micro-g Silicon Accelerometer With CMOS Readout Circuitry

A high-sensitivity, low-noise in-plane (lateral) capacitive silicon microaccelerometer utilizing a combined surface and bulk micromachining technology is reported. The accelerometer utilizes a 0.5-mm-thick, 2.4/spl times/1.0 mm/sup 2/ proof-mass and high aspect-ratio vertical polysilicon sensing electrodes fabricated using a trench refill process. The electrodes are separated from the proof-mass by a 1.1-/spl mu/m sensing gap formed using a sacrificial oxide layer. The measured device sensitivity is 5.6 pF/g. A CMOS readout circuit utilizing a switched-capacitor front-end /spl Sigma/-/spl Delta/ modulator operating at 1 MHz with chopper stabilization and correlated double sampling technique, can resolve a capacitance of 10 aF over a dynamic range of 120 dB in a 1 Hz BW. The measured input referred noise floor of the accelerometer-CMOS interface circuit is 1.6/spl mu/g//spl radic/Hz in atmosphere.

Planarization Processes and Applications: II. B 2 O 3 / P 2 O 5 Doped GeO2 ‐ SiO2 Glasses

Plasma enhanced chemical vapor deposition of boron and phosphorus doped mixed glass films in a horizontal tube reactor using germane , silane , diborane , phosphine , and oxygen has been studied. The glass films offer the potential for both trench refilling and interlevel dielectric applications. Film synthesis was carried out at 200°C using a dual coil inductively coupled plasma system. Oxide film composition was determined using energy dispersive X‐ray spectroscopy and Auger energy spectroscopy. Cross‐sectional scanning electron microscopy was employed for studing the compositional dependency of the reflow behavior of the mixed , , , and glass films over silicon trenches under various ambient atmospheres. Reflow experiments were performed at temperatures ranging from 550 to 800°C in various gas ambient atmospheres. As result of the work, a low temperature (∼600°C) reflow process was developed resulting in fully planar dielectric films. This process may have application for planarization of interlevel dielectrics for ultralarge scale integrated circuits. © 1999 The Electrochemical Society. All rights reserved.

Three-dimensional simulation of an isolation trench refill process

We use EVOLVE-3D to simulate film profile evolution during an isolation trench refill process, focusing on the corner regions of the trench. EVOLVE-3D is a first principles, physically based simulator for low pressure deposition processes, i.e. the chemical reaction rate expressions used were developed from independent experiments. The trenches are refilled using two low pressure deposition processes: (1) low pressure chemical vapor deposition (LPCVD) of silicon dioxide from tetraethoxysilane (TEOS); (2) LPCVD of polysilicon (poly-Si) from silane. Three-dimensional deposition process simulations are used to estimate the film profiles after refilling in the idealized trenches with different aspect ratios. We find that the straight portions close before the trench corners close. If enough poly-Si is deposited to close the corners, the top of the void in the poly-Si moves up as a trench corner is approached. The position dependence of the void top should be considered in the optimization of the trench process, in order to avoid reopening trench corners when the poly-Si is etched back.

Selective Polycrystalline Silicon Growth and Its Applications to Trench Isolation

A selective low temperature polycrystalline silicon growth process has been developed and applied as a dielectric isolation technology to overcome the drawbacks of local oxidation of silicon (LOCOS) for high performance VLSI circuits. By selectively depositing polycrystalline silicon in nitride‐lined trenches using the system, comparatively planar dielectric isolation regions were created upon subsequent oxidation. Oxide‐masked test wafers with variable width trenches were used to exhibit selective polysilicon growth within a production chemical vapor deposition (CVD) reactor. Independent process parameters considered for selective growth optimization included prebake temperature, total reactor pressure, reactor temperature, wafer cleaning procedure, and in situ surface pretreatment procedure. The dependent response variables included surface morphology or planarity, crystallinity, selectivity, and growth rate. X‐ray diffraction, scanning electron microscope (SEM), and transmission electron microscope (TEM) were used to characterize deposition layer surface morphology and crystallinity. A filtered dilute etch combined with a 975°C, 50 Torr prebake effectively removed native oxides and left the surfaces relatively free of foreign matter detrimental to selectivity. Selectivity of approximately 2 particles/mm2 was achieved using this surface preparation technique within a class 1000 clean room. Furthermore, a pretreatment of the surface at 800°C promoted polycrystalline deposition when followed by a 700°C, atmospheric growth step. This investigation has led to a multiple‐step selective polysilicon growth (SPG) process which is repeatable and robust to normal laboratory variations. Advanced bipolar devices isolated by oxidized selective polysilicon trench refill have exhibited leakage currents of only 4.3 pA at a tub‐to‐tub voltage of 20 V. Trench dimensions isolating the active tubs were 2 μm deep, 1 μm wide, and 10 μm long.

A novel trench planarization technique using polysilicon refill, polysilicon oxidation, and oxide etchback

Planarization of polysilicon trench refill by the method of sequential oxidation and oxide etchback is reported. It is shown to result in an excellent wafer surface topography and improved wafer yield compared to the conventional planarization process that utilizes a blanket reactive ion etch removal of the refill. Trench capacitors with varying aspect ratios were fabricated and tested for gate yield, MOS interface characteristics, and gate oxide reliability. The measured MOS interface properties were excellent for trench capacitors planarized using the technique. The wafer yield was in excess of 90%, as compared to less than 65% for the conventional process. The uniformity of the planarization process across 4-in-diameter silicon wafers was also significantly improved. These results demonstrate that the process is attractive for fabricating high-density trench MOS structures in a manufacturing environment. >

Smart-power devices seek wiser CAE tools

The difficulties in developing generalized computer design tools for smart-power semiconductor electronics, a highly specialized field requiring a mix of analog and digital integrated-circuit design, unique semiconductor-device-fabrication technology, and knowledge of application-specific power systems, are examined. These include the problem of dealing with the double-diffused MOS (DMOS) transistor, as well as the simulation of trench refill processes, 2D oxidation phenomena and their stress-induced effects on avalanche breakdown, and the 3D diffusion of the spherical junctions encountered in high-voltage termination. The complexities associated with 2D simulations are discussed in some detail. Dealing with asymmetric devices and with structures consisting of circles, arcs, and 45 degrees angles is also considered.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Single-Wafer RTCVD of Polysilicon: a Complementary Step in Front-End Integrated Processing

AbstractPolycrystalline silicon is used in the fabrication of integrated circuits in various applications. These include a MOS gate material, bipolar emitter and base contacts, trench refill, complementary material for elevated source / drain structures, solid diffusion source for formation of shallow junctions and the active material in thin film transistors. The deposition of polysilicon as the MOS gate electrode or the bipolar emitter contact follows the most critical processing steps in fabrication of these devices. Maximum reproducibility and highest device performance are achieved when the interfaces between the polysilicon and the underneath substrate are well controlled. This level of control can be obtained by combining the compatible processing steps under a controlled environment. Single-wafer RTCVD of polysilicon was introduced to complement the emerging front-end integrated processing technology for MOS, bipolar and BICMOS devices.

Polysilicon Integration

AbstractPolycrystalline silicon has found numerous applications in silicon integrated circuits, initially as a MOS gate material, and later for advanced isolation, capacitor electrodes, resistors, interconnect, bipolar emitters and bases, trench refill, doping sources, and the active material in thin film transistors. Integration of these techniques in a BiCMOS technology requires knowledge of the interactions between the processing steps, and their cumulative effect on the final device and circuit operation. New process techniques also present opportunities for process simplification, added functionality, or improved performance. Examples of polysilicon applications that interact with other process steps and influence device performance are P+ and N+ poly gates and silicidation of gate poly. Silicidation improves circuit speed and provides additional integration opportunities in the form of faster local interconnect, but it may create a problem for older designs with synchronous timing circuitry. More innovative integration of polysilicon includes improved deposition techniques, such as the use of amorphous silicon, “Lo-Hi” poly, in sinat doping, and deposition from disilane sources enable more flexible process design. Other innovations include polysilicon emitters, bases, and buried sinkers in bipolar design, polysilicon sidewall spacers in CMOS, and polysilicon based active transistors for display applications and three dimensional integration.