Trench MOSFET Research Articles

Experimental and Numerical Analysis of Off-State Bias Induced Instabilities in Vertical GaN-on-Si Trench MOSFETs

Experimental and Numerical Analysis of Off-State Bias Induced Instabilities in Vertical GaN-on-Si Trench MOSFETs

High current density 1.2 kV-class HfO2-gated vertical GaN trench MOSFETs

High current density 1.2 kV-class HfO₂-gated vertical GaN trench MOSFETs

Process optimization of wet etching for split gate trench MOSFET

Abstract In this paper, the influence of etching technology on the performance of Split Gate Trench (SGT) MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor) is studied, and the significance and contribution of these improvements in the fields of mechatronics, robotics and control systems are discussed. Etching can be categorized into wet etching and dry etching, with wet etching being widely used for etching the gates of SGT MOSFETs. Due to the isotropic nature of wet etching, issues such as undercutting, trenching, and insufficient link-up region length can arise, leading to short circuits between the gate and the source. The improvement of this problem directly promotes the enhancement of mechatronics system efficiency, the improvement of robot dynamic performance and accuracy, and the realization of efficient control strategies in control systems. By optimizing the process flow to enhance the adhesion of photoresist, increase the density of the HDP (High Density Plasma) deposited oxide film, and adjust the etching rate and frequency of wet etching, it is possible to mitigate the issues of isotropy and insufficient precision in wet etching. These improvements address failure phenomena and enhance product yield.

Impact of Layout Parameter Mismatches on Short Circuit Reliability of Parallel-Connected Planar, Trench, and Double-Trench SiC MOSFETs

Impact of Layout Parameter Mismatches on Short Circuit Reliability of Parallel-Connected Planar, Trench, and Double-Trench SiC MOSFETs

SiC Double Trench MOSFET with Split Gate and Integrated Schottky Barrier Diode for Ultra-Low Power Loss and Improved Short-Circuit Capability

SiC Double Trench MOSFET with Split Gate and Integrated Schottky Barrier Diode for Ultra-Low Power Loss and Improved Short-Circuit Capability

Design of 1.2 kV SiC Double Trench MOSFETs for a Low On-Resistance Through Optimized Current Spreading Layer Concentration

Design of 1.2 kV SiC Double Trench MOSFETs for a Low On-Resistance Through Optimized Current Spreading Layer Concentration

Study of the Bias Driven Threshold Voltage Drift of 1.2 kV SiC MOSFETs in Power Cycling and High Temperature Gate Bias Tests

Threshold voltage instability remains a challenging aspect for metal-oxide semiconductor-field-effect-transistors (MOSFETs) made from silicon carbide (SiC). SiC MOSFETs from two manufacturers, with planar and trench gate structure respectively, have been tested under different test procedures, including power cycling and high temperature gate bias tests. The standard power cycling test setup has been modified to enable an in situ threshold voltage read-out procedure with the hysteresis method. The recorded threshold voltage drift has been compared with results from high temperature gate bias tests applying a simple power law fit, with the intention to predict the drift in power cycling tests. For the group with trench MOSFETs comparable results between power cycling and gate stress tests have been achieved.

Design Optimization and Reliability Evaluation in 1.2 kV SiC Trench MOSFET with Deep P Structure

In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), charge to breakdown (QBD), and time dependent dielectric breakdown (TDDB) tests were conducted. Also, high temperature gate bias (HTGB) and high temperature reverse bias (HTRB) stress tests were carried out for assembled samples to compare device reliability depending on different designs. For the target design, the promising reliability results were confirmed in both wafer level and assembled samples.

Performance enhancement of 4H-SiC superjunction trench MOSFET with extended high-K dielectric

This paper proposes a 4H-SiC superjunction trench MOSFET with extended high-K dielectric under metal gate (EHK SJ-TMOS). The characteristics of EHK SJ-TMOS include the use of the high-K (HK) dielectric as the gate dielectric and the extension of the HK dielectric as a deep trench into the N-type drift region. The extended HK trench effectively modulates the electric field distribution in the SJ drift region, which improves the breakdown voltage (BV). The introduction of HK dielectric also assists in depleting the SJ drift region, which enables the drift region of EHK SJ-TMOS to use a higher doping concentration, thereby reducing Ron,sp. Furthermore, the application of high-K gate dielectric alleviates the high gate oxide electric field problem in conventional SiC superjunction trench MOSFETs (SiC SJ-TMOS). The simulation results demonstrate that EHK SJ-TMOS exhibits a 59.2 % reduction in Ron,sp, a 2.4 % increase in BV, and a 156.5 % improvement in the FOM (FOM = BV2/Ron,sp) compared to the SiC SJ-TMOS, indicating enhanced performance.

Self-clamped P-shield 4H-SiC trench MOSFET for low turn-off loss and suppress switching oscillation

A novel 4H-SiC trench MOSFET with self-clamped P-region (SCP-MOS) is proposed. The breakdown voltage is boosted and switching oscillation is suppressed by introducing a lightly P-type doping concentration region (LP) and additional NCSL. P+ and NCSL form a new electric field modulation region that reduces the electric field at the bottom of the gate, resulting in a higher breakdown voltage for the device. Moreover, When VDS is small, the LP region links P-shield and P+ source region, the P-shield is clamped at a low potential, which effectively reduces the gate to drain capacitance (CGD). As VDS increases, the LP region is gradually depleted, causing the P-shield to transition into floating state, the potential in the P-shield region is raised. Consequently, the described characteristics facilitate achieving low turn-off losses and Surge voltage(VSurge). SCP-MOS has 32 % lower surge voltage compared to GP-MOS and 85 % lower turn-off loss compared to FP-MOS. Overall, SCP-MOS can obtain better EOFF-VSurge trade-off.

Mobility Extraction Using Improved Resistance Partitioning Methodology for Normally-OFF Fully Vertical GaN Trench MOSFETs

In this work, fully vertical GaN trench MOSFETs were fabricated and characterized to evaluate their electrical performances. Transistors show a normally-OFF behavior with a high ION/IOFF (~109) ratio and a significantly small gate leakage current (10−11 A/mm). Thanks to an improved resistance partitioning method, the resistances of the trench bottom and trench channel were extracted accurately by taking into account different charging conditions. This methodology enabled an estimation of the effective channel and bottom mobility of 11.1 cm2/V·s and 15.1 cm2/V·s, respectively.

SiC Fin-Channel MOSFET for Enhanced Gate Shielding Effect

A SiC fin-channel MOSFET structure (Fin-MOS) is proposed for an enhanced gate shielding effect. The gates are placed on each side of the narrow fin-channel region, while grounded p-shield regions below the gates provide a strong shielding effect. The device is investigated using Sentaurus TCAD. For a narrow fin-channel region, there is difficulty in forming an Ohmic contact to the p-base; a floating p-base might potentially store negative charges upon high drain voltage, and, thus, causes threshold voltage instabilities. The simulation reveals that, for a fin-width of 0.2 μm, the p-shield regions provide a stringent shielding effect against high drain voltage, and the dynamic threshold voltage shift (∆Vth) is negligible. Compared to conventional trench MOSFET (Trench-MOS) and asymmetric trench MOSFET (Asym-MOS), the proposed Fin-MOS boasts the lowest OFF-state oxide field and reverse transfer capacitance (Crss), while maintaining a similar low ON-resistance.

Investigations of 4H‐SiC trench MOSFET with integrated high‐K deep trench and gate dielectric

AbstractThis paper proposes and investigates a novel 4H‐SiC trench MOSFET (TMOS) with integrated high‐K deep trench and gate dielectric (INHK‐TMOS). The integrated high‐K (INHK) consists of a high‐K gate dielectric and an extended high‐K deep trench dielectric in the drift region. Firstly, the high‐K gate dielectric together with the metal‐forming high‐K metal gate structure, which increases the gate oxide capacitance (COX), reduces the threshold voltage (VTH) and the specific on‐resistance (Ron,sp). Secondly, the extended high‐K deep trench dielectric not only modulates the electric field in the drift region by introducing a new electric field peak at the bottom of the high‐K deep trench dielectric, thereby enhancing the breakdown voltage (BV), but also improves the doping concentration (ND) of the drift region by the assist depletion effect of the high‐K dielectric, further optimizing the forward conduction characteristics. Simulation results demonstrate that when compared to the conventional TMOS, the INHK‐TMOS using HfO2 exhibits a 52.6% reduction in VTH, a 52.1% reduction in Ron,sp, a 20.3% increasement in BV and a 202.3% improvement in figure of merit.

SiC superjunction MOSFET with Schottky diode for improving short-circuit and reverse recovery ruggedness

In this article, a novel SiC superjunction MOSFET with Schottky diode containing N- and P-type barrier is proposed to improving short-circuit and reverse recovery ruggedness, investigated by TCAD simulations. The adoption of superjunction and p-shields structure can reduce saturation current, and thus, improve short-circuit capability. A fine gate oxide providing long-term reliability of the device is obtained. Also, N-type Schottky diode for electrons is used to dampen bipolar conduction of the parasitic body diode, while P-type Schottky diode for holes is introduced to constrain the hole inflow and extraction attributed to the transient variation of the superjunction. As a result, compared with an SBD-wall-integrated trench MOSFET (SWITCH-MOS), a low on-resistance and high breakdown voltage of the proposed structure are gained. More importantly, the proposed device exhibits stronger temperature-dependent immunity. As expected, simulation results indicate that the proposed device under 10 nH stray inductance shows a 30%–50 % reduction in the peak reverse recovery current and a 50%–70 % decrease in the current rising slope of reverse recovery, compared to only a single superjunction, when the metal workfunction varies from 5.1 to 5.6 eV. Moreover, the short-circuit withstanding time of the proposed structure increases roughly 2 times longer than that of SWITCH-MOS.

The GaN trench MOSFET with adaptive voltage tolerance achieved through a dual-shielding structure

A novel GaN trench gate vertical MOSFET (PSGT-MOSFET) with a double-shield structure composed of a separated gate (SG) and a p-type shielding layer (P_shield) is proposed and investigated. The P_shield is positioned within the drift region, which can suppress the electric field peak at the bottom of the trench during the off state. This helps to prevent premature breakdown of the gate oxide layer. Additionally, the presence of P_shield enables the device to have adaptive voltage withstand characteristics. The SG can convert a portion of gate-to-drain capacitance (C gd) into drain-to-source capacitance (C ds), significantly reducing the gate-to-drain charge of the device. This improvement in charge distribution helps enhance the switching characteristics of the device. Later, the impact of the position and length of the P_shield on the breakdown voltage (BV) and specific on-resistance (R on_sp) was studied. The influence of the position and length of the SG on gate charge (Q gd) and BV was also investigated. Through TCAD simulations, the parameters of P_shield and SG were optimized. Compared to conventional GaN TG-MOSFET with the same structural parameters, the gate charge was reduced by 88%. In addition, this paper also discusses the principle of adaptive voltage withstand in PSGT-MOSFET.

Physical insights into trapping effects on vertical GaN-on-Si trench MOSFETs from TCAD

Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications. Being still in an early development phase, vertical GaN devices are yet to be fully optimized and require careful studies to foster their development. In this work, we report on the physical insights into device performance improvements obtained during the development of vertical GaN-on-Si trench MOSFETs (TMOS’s) provided by TCAD simulations, enhancing the dependability of the adopted process optimization approaches. Specifically, two different TMOS devices are compared in terms of transfer-curve hysteresis (H) and subthreshold slope (SS), showing a ≈ 75% H reduction along with a ≈ 30% SS decrease. Simulations allow attributing the achieved improvements to a decrease in the border and interface traps, respectively. A sensitivity analysis is also carried out, allowing to quantify the additional trap density reduction required to minimize both figures of merit.

Fabricating and TCAD Optimization for a SiC Trench MOSFET With Tilted P-Shielding Implantation and Integrated TJBS

Fabricating and TCAD Optimization for a SiC Trench MOSFET With Tilted P-Shielding Implantation and Integrated TJBS

A novel split-gate trench MOSFET embedded with a high-k pillar for higher breakdown voltage

A novel split-gate trench MOSFET embedded with a high-k pillar (HKP SGT-MOS) is proposed in this study. Numerous electric displacement lines are allowed to enter the high-k pillar introduced beneath the split gate, thus relieving the crowding of the electric field at the bottom corner of the split gate. Therefore, the HKP SGT-MOS can achieve a higher breakdown voltage (BV) without sacrificing its forward conduction. Various dielectrics for the high-k pillar, such as SiO2, Si3N4, Al2O3 and HfO2, are investigated. The results reveal that HfO2 has the largest figure of merit (FOM) and BV. The characteristics of the HKP SGT-MOS have also been validated by the Technology Computer-Aided Design simulation, and the BV and (FOM = BV 2/R on,sp) are 258.3 V and 37.46 MW cm−2, achieving 36.7% and 87.02% improvement compared to the conventional SGT-MOS (CSGT-MOS), and 18.4% and 38.59% improvement compared to the SGT-MOS with short split-gate (SSGT-MOS). Moreover, the influence of the drift doping concentration, the mesa width, the length of the drift region and the width of the split gate/high-k pillar are also studied to optimize the proposed HKP SGT-MOS.

Novel SiC Trench MOSFET with Improved Third-Quadrant Performance and Switching Speed.

A SiC double-trench MOSFET embedded with a lower-barrier diode and an L-shaped gate-source in the gate trench, showing improved reverse conduction and an improved switching performance, was proposed and studied with 2-D simulations. Compared with a double-trench MOSFET (DT-MOS) and a DT-MOS with a channel-MOS diode (DTC-MOS), the proposed MOS showed a lower voltage drop (VF) at IS = 100 A/cm2, which can prevent bipolar degradation at the same blocking voltage (BV) and decrease the maximum oxide electric field (Emox). Additionally, the gate-drain capacitance (Cgd) and gate-drain charge (Qgd) of the proposed MOSFET decreased significantly because the source extended to the bottom of the gate, and the overlap between the gate electrode and drain electrode decreased. Although the proposed MOS had a greater Ron,sp than the DT-MOS and DTC-MOS, it had a lower switching loss and greater advantages for high-frequency applications.

Investigation on gate oxide reliability under gate bias screening for commercial SiC planar and trench MOSFETs

This paper evaluates the impact of the fast high gate-voltage screening technique on gate oxide reliability of commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The measurements are conducted on packaged devices with the intent that the results will be applicable to wafer-level screening. The threshold voltage (Vth) of SiC MOSFETs is measured before and after various screening treatments and recovery process. In addition, constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on SiC MOSFETs to obtain the intrinsic lifetime of gate oxide. The objective of this study is to determine the optimal screening conditions and improve screening efficiency without degradation of gate oxide reliability, such as Vth shift and reduced oxide intrinsic lifetime. Due to the differences in the gate oxidation process and structural design of SiC planar and trench MOSFETs, the two types of devices exhibit different oxide reliability in the screening process. The recommended screening conditions obtained in this paper reveal that SiC trench MOSFETs can accept higher screening voltages compared to SiC planar MOSFETs. Hence, it can be concluded that more efficient screening techniques can be adopted for SiC MOSFETs with thicker gate oxide to meet the requirements of industrial applications.