Trench MOSFET Research Articles

Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

The yield of high power 4H-SiC Trench-MOSFET devices, especially for those with large chip area, is largely dependent on the quality of the underlying epitaxial layers and therefore low densities of critical defects are of utmost importance. Different growth conditions for the deposition of epitaxial layers were investigated to reduce the impact of defects on electrical device performance. For this investigation, 12 μm thick n-type epitaxial layers were grown varying growth rates for the buffer and the drift layer in a warm-wall chemical vapor deposition reactor. The defects in the epitaxial layers were characterized utilizing surface microscopy as well as ultraviolet photoluminescence techniques. A quantitative comparison of surface defects and crystallographic defects between the different growth conditions was conducted with these methods. The impact of the growth conditions on the formation of critical defects is discussed in detail. The reduction of critical defects, which resulted in an increase of the predicted die yield, as well as an outlook on future investigations, is discussed.

Novel SiC SBD-wall-integrated trench MOSFET with a semi-superjunction and split trench gate

Novel SiC SBD-wall-integrated trench MOSFET with a semi-superjunction and split trench gate

A comparative analysis and an optimized structure of vertical GaN floating gate trench MOSFET for high-frequency FOM

A vertical GaN floating gate trench MOSFET (FG-MOSFET) device structure has been optimized to obtain an enhanced high-frequency figure of merit (HF-FOM) than the conventional SGT- and TG-MOSFET. The floating gate (FG) electrode helps to reduce the surface electric field and binges in the middle of the drift layer. Using TCAD simulation, we demonstrate that with proper design of trench depth, drift doping, and field plate oxide thickness, the corresponding electric-field distribution for FG-MOSFET can be reduced to 2.3 MV cm−1. The proposed device has been designed for 600 V blocking voltage capability and with a specific on-resistance () as low as 0.73 mΩ cm2 due to the higher drift doping concentration. The HF-FOM () of FG-MOSFET shows a lower by two times and four times compared to SGT- and TG-MOSFET, due to FP oxide. Our results show that the FG-MOSFET device produces 15% and 47% reductions in the switching energy losses when compared with the similar current rated SGT- and TG-MOSFET devices, respectively.

Degradation of 650 V SiC double-trench MOSFETs under repetitive overcurrent switching stress

In this paper, the ruggedness of 650 V SiC double–trench MOSFETs (DT-MOS) under repetitive overcurrent switching stress was evaluated and investigated experimentally. The devices under test (DUTs) were electrically stressed by the hard switching transient as well as the conduction current nearly four times the rated one. It was shown that the threshold voltage (VTH) and on-resistance (RON) of DUTs increased after 100 K stress cycles, indicating the occurrence of performance deterioration. TCAD simulations revealed a similar failure mechanism with HTGB that the electrons injection into the gate oxide during the conduction stage should take the responsibility, which is totally different from the case of SiC planar-gate ones. What's more, the dependence of such degradation on the conduction duration TCD, overcurrent level IOL, driving condition VGS(ON/OFF) and gate resistors RG(ON/OFF) was researched comprehensively. The findings in this paper could provide indications to better drive such state-of-the-art SiC DT-MOS for long-term use in power electronic applications.

A Figure of Merit for Selection of the Best Family of SiC Power MOSFETs

This paper proposes a criterion to select the best family of commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs) that provides the highest quality and reliability. Applying a recently published integrated-charge method, a newly proposed figure of merit is correlated to the density of near-interface traps that degrade the quality and reliability of SiC MOSFETs. The applicability of the proposed figure of merit is experimentally demonstrated with the most widely used and commercially available planar and trench MOSFETs from different manufacturers.

On-State Voltage Drop Analytical Model for 4H-SiC Trench IGBTs

In this paper, a model for the forward voltage drop in a 4H-SiC trench IGBT is developed. The analytical model is based on the 4H-SiC trench MOSFET voltage model and the hole-carrier concentration profile in the N-drift region for a conventional 4H-SiC trench IGBT. Moreover, an on-state voltage drop analytical model is validated using a 2D numerical simulation, and the simulation results demonstrate that there is good agreement between the ATLAS simulation data and analytic solutions.

Hot carrier reliability assessment of vacuum gate dielectric trench MOSFET (TG-VacuFET)

Hot carrier reliability assessment of vacuum gate dielectric trench MOSFET (TG-VacuFET)

A 1200 V SiC Trench MOSFET with a Laterally Widened P-Shield Region to Enhance the Short-Circuit Ruggedness

In this paper, a novel 1200 V SiC trench MOSFET with a laterally widened P-shield region (LW-MOSFET) is presented by using the two-dimensional numerical simulation. Compared with the conventional trench MOSFET (CT-MOSFET), the LW-MOSFET demonstrates an effective enhancement on the short-circuit (SC) reliability and the optimization of static performance simultaneously. According to the simulation results, the SC withstand time (SCWT) of the LW-MOSFET at 600 V DC bus voltage can reach 8 μs, while that of the CT-MOSFET is only 3 μs at the same conditions. The main reason is that the laterally widened P-shield region can help to suppress the saturation current and mitigate the huge current accumulation near the trench area, leading to an enhancement of the SC reliability. Moreover, the Baliga’s FOM of the proposed structure is improved by 45.7%, which benefits from the higher breakdown voltage (BV) and the lower specific on-state resistance (Ron, sp) by using the optimized structure. The advantage of static performance is related to the local charge balance behavior provided by the laterally widened P-shield region, which helps to use a higher doped current spread layer (CSL) without bringing a degeneration of BV.

Degradation and breakdown behaviors of SGTs under repetitive unclamped inductive switching avalanche stress

The repetitive unclamped inductive switching (UIS) avalanche stress is conducted to investigate the degradation and breakdown behaviors of conventional shield gate trench MOSFET (C-SGT) and P-ring SGT MOSFETs (P-SGT). It is found that the static and dynamic parameters of both devices show different degrees of degradation. Combining experimental and simulation results, the hot holes trapped into the Si/SiO2 interface and the increase of crystal lattice temperature should be responsible for the degradation and breakdown behaviors. Moreover, under repetitive UIS avalanche stress, the reliability of P-SGT overcomes that of C-SGT, benefitting from the decreasing of the impact ionization rate at bottom of field oxide caused by the existence of P-ring.

Improvement on short-circuit ability of SiC super-junction MOSFET with partially widened pillar structure

A novel 1200 V SiC super-junction (SJ) MOSFET with a partially widened pillar structure is proposed and investigated by using the two-dimensional numerical simulation tool. Based on the SiC SJ MOSFET structure, a partially widened P-region is added at the SJ pillar region to improve the short-circuit (SC) ability. After investigating the position and doping concentration of the widened P-region, an optimal structure is determined. From the simulation results, the SC withstand times (SCWTs) of the conventional trench MOSFET (CT-MOSFET), the SJ MOSFET, and the proposed structure at 800 V DC bus voltage are 15 μs, 17 μs, and 24 μs, respectively. The SCWTs of the proposed structure are increased by 60% and 41.2% in comparison with that of the other two structures. The main reason for the proposed structure with an enhanced SC capability is related to the effective suppression of saturation current at the high DC bias conditions by using a modulated P-pillar region. Meanwhile, a good Baliga’s FOM (BV 2/R on) also can be achieved in the proposed structure due to the advantage of the SJ structure. In addition, the fabrication technology of the proposed structure is compatible with the standard epitaxy growth method used in the SJ MOSFET. As a result, the SJ structure with this feasible optimization skill presents an effect on improving the SC reliability of the SiC SJ MOSFET without the degeneration of the Baliga’s FOM.

Visualization of local strain in 4H-SiC trench metal-oxide-semiconductor field-effect transistor using synchrotron nanobeam X-ray diffraction

We investigated the local strain in a silicon carbide (4H-SiC) (0001) trench metal-oxide semiconductor field-effect transistor (MOSFET) using synchrotron nanobeam X-ray diffraction (nano-XRD) at the SPring-8 BL13XU beamline. Using X-rays incident on the 4H-SiC trench cross section, diffraction measurements were performed on the and planes. Intensity maps of the and diffractions yielded images reflecting the trench structure. The spatial resolution of the 4H-SiC intensity map in the [0001] direction was higher than that for the diffraction because the angle of incidence was close to perpendicular to the sample. From two-dimensional reciprocal space maps of the symmetric and asymmetric diffractions, the tilt and the - and (0004)-plane strain components were individually separated and visualized. A tensile strain of approximately 0.1% was found in the region between the trenches. These results indicate the effectiveness of nano-XRD for strain visualization in trench MOSFETs and similar electronic devices.

Enhancement of channel mobility in 4H-SiC trench MOSFET by inducing stress at SiO2/SiC gate interface

To investigate the impact of stress at the SiO2/SiC gate interface on the channel mobility of 4H-SiC trench MOSFETs, we fabricated trench MOSFETs with two variations of stress in the channel region by changing the deposition temperature of polycrystalline silicon used for gate electrodes. The results found that effective mobility was enhanced by several dozen MPa of tensile stress toward induced by the polycrystalline silicon. Based on the temperature dependence of mobility, all scattering mobilities were enhanced. It was supposed that the electron effective mass decreased because of tensile stress induced at the channel region.

High performance 4H-SiC MOSFET with deep source trench

In this study, we investigated a 4H-SiC deep source trench metal-oxide semiconductor field-effect transistor (DST-MOSFET) using technology computer-aided design numerical simulations. The proposed DST-MOSFET comprises a P-pillar formed along with the DST and a side P+ shielding region (SPR), which replaces the gate trench bottom SPR. Owing to the superjunction generated by the P-pillar and N-drift region, the static characteristics of the DST-MOSFET were superior to those of the trench gate MOSFET (UMOSFET) and double-trench MOSFET (DT-MOSFET). The specific on-resistance and Baliga’s figure of merit of DST-MOSFET improved by 9% and 104%, respectively, in comparison with those of UMOSFET; and by 37% and 64%, respectively, compared to those of DT-MOSFET. Additionally, the SPR reduced the gate-to-drain capacitance of the DST-MOSFET and improved the switching characteristics. Consequently, the total switching energy loss of the proposed DST-MOSFET reduced by 63% and 47% in comparison with those of the UMOSFET and DT-MOSFET, respectively.

Impact of Negative Gate Bias and Inductive Load on the Single-Pulse Avalanche Capability of 1200-V SiC Trench MOSFETs

In this study, the single-pulse avalanche capability of two types of 1.2-kV silicon carbide (SiC) trench MOSFETs was investigated through unclamped inductive switching (UIS) testing and numerical TCAD simulation. It was found that the UIS failure mechanisms differed in the two MOSFETs. In the asymmetric trench MOSFET, the failure was caused by high temperature, which can damage the SiC layer during the UIS transient, whereas in the double-trench MOSFET, the failure was caused by a high electric field concentration at the trench gate bottom oxide, and the physical damage was confirmed by optical beam induced resistance change (OBIRCH) and scanning electron microscopy (SEM) cross-sectional analysis. In addition, the UIS-based local damage phenomenon was investigated with varying inductance. Nonuniform contact resistance may have been a cause of the avalanche current concentration.

SiC Heterojunction Trench MOSFET with a Buried P-Type Pillar for the Low Gate-Drain Charge and Switching Loss.

A novel Silicon-Carbide heterojunction U-MOSFET embedded a P-type pillar buried in the drift layer (BP-TMOS) is proposed and simulated in this study. When functioning in the on state, the merged heterojunction structure will control the parasitic body diode, and the switching loss will decrease. Moreover, to lighten the electric field on the gate oxide corner, a high-doped L-shaped P+ layer near the heterojunction beneath the gate oxide was introduced; thus, the gate oxide reliability improved. A p-type pillar is introduced in the drift layer. The p-type pillar can assistant the drift layer to deplete. Thus, the specific on-resistance for BP-TMOS can be reduced with an increase in the N-drift region’s doping concentration. Compared to the traditional SiC MOSFET (C-TMOS), the specific on-resistance decreased by 20.4%, and the breakdown voltage increased by 53.7% for BP-TMOS, respectively. Meanwhile the device exhibits a 55% decrease and a 69.7% decrease for the switching loss and gate to drain charge.

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistor (MOSFET) structure with side-wall p-type pillar (p-pillar) and wrap n-type pillar (n-pillar) in the n-drain was investigated by utilizing Silvaco TCAD simulations. The optimized structure mainly includes a p+ buried region, a light n-type current spreading layer (CSL), a p-type pillar region, and a wrapping n-type pillar region at the right and bottom of the p-pillar. The improved structure is named as SNPPT-MOS. The side-wall p-pillar region could better relieve the high electric field around the p+ shielding region and the gate oxide in the off-state mode. The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance (R on,sp). As a result, the SNPPT-MOS structure exhibits that the figure of merit (FoM) related to the breakdown voltage (V BR) and R on,sp () of the SNPPT-MOS is improved by 44.5%, in comparison to that of the conventional trench gate SJ MOSFET (full-SJ-MOS). In addition, the SNPPT-MOS structure achieves a much faster-witching speed than the full-SJ-MOS, and the result indicates an appreciable reduction in the switching energy loss.

Investigation of SiC Trench MOSFETs' Reliability under Short-Circuit Conditions.

In this paper, the short-circuit robustness of 1200 V silicon carbide (SiC) trench MOSFETs with different gate structures has been investigated. The MOSFETs exhibited different failure modes under different DC bus voltages. For double trench SiC MOSFETs, failure modes are gate failure at lower dc bus voltages and thermal runaway at higher dc bus voltages, while failure modes for asymmetric trench SiC MOSFETs are soft failure and thermal runaway, respectively. The shortcircuit withstanding time (SCWT) of the asymmetric trench MOSFET is higher than that of the double trench MOSFETs. The thermal and mechanical stresses inside the devices during the short-circuit tests have been simulated to probe into the failure mechanisms and reveal the impact of the device structures on the device reliability. Finally, post-failure analysis has been carried out to verify the root causes of the device failure.

Electrical Performances of GaN-based Vertical Trench MOSFETs with Cylindrical and Hexagonal Structure

In this paper, we designed and analyzed the electrical performances of gallium-nitride (GaN)-based vertical trench metal-oxide-semiconductor field-effect-transistors (MOSFETs) using three-dimensional technical computer-aided design (3-D TCAD) simulation. The cylindrical device is generally considered as superior device than the polygonal devices because it has better gate controllability. In the case of GaN-based vertical devices, however, the cylindrical device performs inferiorly to the hexagonal device in terms of crystal directions for the GaN sidewall plane such as m-plane (1-100), a-plane (11-20), and c-plane (0001). The simulation results provide an understanding and design guidelines for which electrical properties of trench FETs are affected by cross-section shape.

SiC Fin-Shaped Gate Trench MOSFET with Integrated Schottky Diode.

A silicon carbide (SiC) trench MOSFET featuring fin-shaped gate and integrated Schottky barrier diode under split P type shield (SPS) protection (FS-TMOS) is proposed by finite element modeling. The physical mechanism of FS-TMOS is studied comprehensively in terms of fundamental (blocking, conduction, and dynamic) performance and transient extreme stress reliability. The fin-shaped gate on the sidewall of the trench and integrated Schottky diode at the bottom of trench aim to the reduction of gate charge and improvement on the third quadrant performance, respectively. The SPS region is fully utilized to suppress excessive electric field both at trench oxide and Schottky contact when OFF-state. Compared with conventional trench MOSFET (C-TMOS), the gate charge, Miller charge, Von at third quadrant, Ron,sp·Qgd, and Ron,sp·Qg of FS-TMOS are significantly reduced by 34%, 20%, 65%, 0.1%, and 14%, respectively. Furthermore, short-circuit and avalanche capabilities are discussed, verifying the FS-TMOS is more robust than C-TMOS. It suggests that the proposed FS-TMOS is a promising candidate for next-generation high efficiency and high-power density applications.

Mechanisms and characteristics of a low-loss split gate trench MOSFET with shield layer

In this work, a split gate trench MOSFET (SGT) with shield layer (SL) is proposed to improve electrical characteristics. The SL modulates charge division of ionized donor atoms in drift region during depletion spreading. As a result, ionized donors electrically coupled to gate are dramatically reduced, thus lowering gate-drain charge (QGD). On the other hand, the SL structure increases energy band of channel region to address drain induced barrier lowering (DIBL) issue while maintaining a lower channel length and doping concentration. Significant reductions in on-resistance (RON), gate charge (QG), and total power losses are confirmed by simulations. The proposed SGT with SL achieves a switching figure of merit (RON × QG) of 30.46 mΩnC, which is 35.5% smaller than conventional trench MOSFET technology, but almost without impacting other fundamental parameters.