Trench Gate Metal Oxide Semiconductor Research Articles

Dependence of reverse leakage on the edge termination process in vertical GaN power device

The trench gate metal oxide semiconductor field effect transistor (MOSFET) represents a prominent device architecture among the Gallium Nitride (GaN) based vertical devices currently investigated for the next generation of power electronics. A low leakage current level in off-state under high drain bias is of great importance for vertical transistors since it is a crucial feature for high breakdown voltage and device reliability. The off-state drain leakage originates from different sources in the vertical trench gate MOSFET. Besides the trench gate module, the leakage paths at the dry-etched sidewall of the lateral edge termination can also significantly contribute to the off-state drain-current. In this report, the influence of each relevant process step on the drain leakage current in off-state that is related to the lateral edge termination is investigated utilizing specific test structures on high-quality GaN epitaxial material which mimic the lateral edge termination of the MOSFET. Electrical characterization reveals the sensitivity of the leakage current to plasma-related processes. A termination technology is presented that results in low leakage current while including thick dielectric layers from plasma-assisted deposition as intended for fabrication of a field plate structure over the edge termination.

A 4H-SiC semi-super-junction shielded trench MOSFET: p-pillar is grounded to optimize the electric field characteristics

A 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor (UMOSFET) with semi-super-junction shielded structure (SS-UMOS) is proposed and compared with conventional trench MOSFET (CT-UMOS) in this work. The advantage of the proposed structure is given by comprehensive study of the mechanism of the local semi-super-junction structure at the bottom of the trench MOSFET. In particular, the influence of the bias condition of the p-pillar at the bottom of the trench on the static and dynamic performances of the device is compared and revealed. The on-resistance of SS-UMOS with grounded (G) and ungrounded (NG) p-pillar is reduced by 52% (G) and 71% (NG) compared to CT-UMOS, respectively. Additionally, gate oxide in the GSS-UMOS is fully protected by the p-shield layer as well as semi-super-junction structure under the trench and p-base regions. Thus, a reduced electric-field of 2 MV/cm can be achieved at the corner of the p-shield layer. However, the quasi-intrinsic protective layer cannot be formed in NGSS-UMOS due to the charge storage effect in the floating p-pillar, resulting in a large electric field of 2.7 MV/cm at the gate oxide layer. Moreover, the total switching loss of GSS-UMOS is 1.95 mJ/cm2 and is reduced by 18% compared with CT-UMOS. On the contrary, the NGSS-UMOS has the slowest overall switching speed due to the weakened shielding effect of the p-pillar and the largest gate-to-drain capacitance among the three. The proposed GSS-UMOS plays an important role in high-voltage and high-frequency applications, and will provide a valuable idea for device design and circuit applications.

Improved 4H-SiC UMOSFET with super-junction shield region* *Project supported by the National Natural Science Foundation of China (Grant Nos. 61774052 and 61904045), the Youth Foundation of the Education Department of Jiangxi Province, China (Grant No. GJJ191154), and the Youth Foundation of Ping Xiang University, China (Grant No. 2018D0230).

This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor (MOSFET) (UMOSFET) fitted with a super-junction (SJ) shielded region. The modified structure is composed of two n-type conductive pillars, three p-type conductive pillars, an oxide trench under the gate, and a light n-type current spreading layer (NCSL) under the p-body. The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer, thus improving the specific on-resistance (R on,sp). There are three p-type pillars in the modified structure, with the p-type pillars on both sides playing the same role. The p-type conductive pillars relieve the electric field (E-field) in the corner of the trench bottom. Two-dimensional simulation (silvaco TCAD) indicates that R on,sp of the modified structure, and breakdown voltage (V BR) are improved by 22.2% and 21.1% respectively, while the maximum figure of merit () is improved by 79.0%. Furthermore, the improved structure achieves a light smaller low gate-to-drain charge (Q gd) and when compared with the conventional UMOSFET (conventional-UMOS), it displays great advantages for reducing the switching energy loss. These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance, which also enables the charge carriers to be extracted quickly. In the end, under the condition of the same total charge quantity, the simulation comparison of gate charge and OFF-state characteristics between Gauss-doped structure and uniform-doped structure shows that Gauss-doped structure increases the V BR of the device without degradation of dynamic performance.

Comprehensive Characterization of the 4H-SiC Planar and Trench Gate MOSFETs From Cryogenic to High Temperature

In this article, the static, dynamic, and short-circuit properties of 1.2-kV commercial 4H-SiC planar and trench gate metal–oxide–semiconductor field-effect transistors (MOSFETs) are compared and analyzed in a wide temperature range from 90 to 493 K. The temperature-dependent specific ON-resistance ( ${R}_{\text {sp}- \mathrm{\scriptscriptstyle ON}}$ ) and threshold voltage ( ${V}_{\text {th}}$ ) are analyzed in relation to the density of the interface state. The turn-on rise and turn-off fall times ( ${T}_{r}$ and ${T}_{f}$ ) and the corresponding energy loss ( ${E}_{r}$ and ${E}_{f}$ ) are extracted from a double-pulse test from cryogenic to high temperature and analyzed. The short-circuit capability of the two structures is studied at low temperature for the first time. The comprehensive comparison and analysis of the planar and trench gate MOSFET versus temperature in this work show the importance to study applications with SiC MOSFETs in a wide temperature range, especially for the cryogenic temperatures.

(Invited) A Discussion on the Latest Performance of Gan–Based Vertical Devices and the Paths Forward

Recent progress in vertical Gallium Nitride (GaN)-based power electronic devices has been compelling. Thanks to dedicated programs like the ARPA-E SWITCHES, which led to the understanding of the challenges, while enabling several variants of vertical devices to be studied and compared. An overview of different flavors of vertical devices and their latest performance will be presented. Under the SWITCHES program, in collaboration with UCSB, NRL and Transphorm, we pursued two novel and practical approaches that had the common theme of markedly reducing the required device chip size compared to commercially available lateral GaN-on-Si HEMTs. CAVET [1,2] was investigated where the gated region was implemented with p-type layer on an n-channel. The study allowed us to understand the limitation of an ion-implanted current blocking layer in a 3-terminal vertical FET configuration, eliminating restrictions imposed by poor gate dielectric. In order to achieve a ‘true’ vertical transistor, OGFET, a variant of MOSFET, was developed [3,4] where, unlike the CAVET, the gating was also performed on electrons traveling perpendicular to the surface. From a CAVET, we have successfully achieved dispersion-less switching under 500ns pulses (under Pulsed I-V measurements), and over 1100V blocking in OGFET where scaling of the devices to 1A was recently achieved. While the successes of these devices speak volumes about the future possibilities and roadmap, the technical challenges are substantial. The overarching issue is related to the realization of a well-behaved buried p-n junction, which forms the basic building block of most vertical transistors for power electronics. Fundamentally, all of them require Mg based doping, and therefore the issues related to Mg activation in GaN impact everyone. Mg is a deep acceptor in GaN offering less than 1% activation under room temperature. In addition to the RT ionization related challenges, buried p-GaN activation (this strictly means the activation from hydrogen that tend to form Mg-H complexes passivating the acceptors) is a proven concern. In short, the difficulties in achieving well-behaved buried p-GaN have stunted the possibility of realizing well-behaved (buried) p-n junctions critical to vertical devices. In a MOSFET the p-layer is grown during the initial growth of the structure. This guarantees a well-behaved p-type GaN. Similar to the reports by various groups like Toyoda Gosei and HRL[5,6], Gupta et al. (UCSB) [4] showed via OGEFT that trenched vertical devices deliver promisingly high voltage results with a path towards low On-resistance (Ron). Recently Ji et al (UC Davis) [7] successfully delivered scaled devices capable of offering 1A current with 144 unit cells in parallel. Ron <4.4mΩ.cm2 was achieved in these devices, which can be lowered further with improvement in the channel mobility. Normally-off in design, the MOSFETs definitely are attractive for the economic use of the chip area and their compatibility with presently used gate drivers A parameter to address with future research is the channel mobility to deliver lower Ron. While the typical behavior of a good gate oxide (like low trapping and small threshold voltage (Vth) shifts) also apply for these devices, the gates being designed on the sidewalls (being a or m-plane) ensure higher threshold voltages compared to c-plane HEMTs or CAVETs. This definitely alleviates the well-known tradeoff of Ron and threshold Vth to a vast degree. This talk will go over all the major achievements made over the last three years, and lay out the challenges for achieving 1.2KV switches with Ron<3mΩ.cm2 S. Chowdhury, et al., “CAVET on bulk GaN substrates achieved with MBE-regrown AlGaN/GaN layers to suppress dispersion,” IEEE Electron Device Lett., vol. 33, no. 1, pp. 41-43, Jan. 2012.S. Mandal, et al., “All-GaN Mg ion-implanted current blocking layer CAVET demonstrating over 500V blocking voltage,” in International Workshop on Nitride Semiconductors (IWN), Orlando, USA, 2016.W. Li, et al., “Design and fabrication of a 1.2kV GaN-based MOS vertical transistor for single chip normally off operation,” Phys. Status Solidi A., vol. 213, no. 10, pp.2714-2720, Oct. 201C. Gupta, et al., “OG-FET: An in- situ Oxide, GaN interlayer based vertical trench MOSFET,” IEEE Trans. Electron Devices., vol. 37 , no. 12, pp. 1601-1604, Oct. 2016.H. Otake, et al., "Vertical GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistors on GaN Bulk Substrates", Applied Physics Express, vol. 1, no. 1, p. 011105, 2008.R. Li, et al., "600 V/ 1.7 Ω Normally-Off GaN Vertical Trench Metal–Oxide–Semiconductor Field-Effect Transistor", IEEE Electron Device Letters, vol. 37, no. 11, pp. 1466-1469, 2016.D.Ji et.al, "Scaling GaN OGFET with MOCVD regrown n-GaN insert layer as the channel", 75th Annual Device Research Conference (DRC), Jun. 2017.

3.3-kV-Class 4H-SiC MeV-Implanted UMOSFET With Reduced Gate Oxide Field

A critical issue for SiC trench gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) is gate oxide shielding from the electric field at the trench bottom. In this letter, low ON-resistance with low gate electric field was achieved in a 3.3-kV-class UMOSFET with a unique hexagonal buried p-base region formed by MeV ion implantation. The shielding effect was further enhanced by a self-aligned trench bottom shielding region. The specific ON-resistance, with and without the trench bottom shielding region, was 8.3 and 9.4 $\text {m}\Omega \text {cm}^{2}$ , respectively. The blocking voltage in each case was $\sim 3800$ V. The electric field in the gate oxide with the trench bottom shielding region was reduced to 2.5 MV/cm at 3300 V.

A novel trench gate MOSFET with a multiple-layered gate oxide for high-reliability operation

Gate dielectrics in trench structures for trench gate metal oxide semiconductor field-effect transistor (MOSFET) power devices are very important to realize excellent characteristics. In this paper we describe multiple-layer gate dielectrics for trench gate MOSFETs with both thermal and chemical vapor deposition (CVD) gate oxides that exhibit excellent gate oxide properties and surface roughness. Through various trench etching experiments for better surface conditions in the trench, the optimum etching gas chemistry and etch conditions were found. The destruction of gate dielectric in trench gate MOSFET occurs at the top and the bottom trench corner edges. The structure of the gate electrode is pulled out with the polysilicon layer which is buried in the trench. Thus, high electric field operation is inevitable at the gate between source diffusion and the gate polysilicon. Moreover, the trench corner oxide suffers from the high electric field. We propose a multiple-gate dielectric structure of a thermal oxide and CVD oxide for highly reliable operation of the device. This enables trench surface smoothing and low thermal stress at the trench corners and provides the oxide thickness uniformity, giving superior device characteristics of high breakdown voltage and low leakage current. These improvements are caused by the excellent quality of the gate oxide and the good thickness uniformity that is formed at the inner trench with a specific geometrical factor.

Improvement of floating island and thick bottom oxide trench gate metal–oxide–semiconductor field-effect transistor

A metal–oxide–semiconductor field-effect transistor (MOSFET) structure called FITMOS (floating island and thick bottom oxide trench gate MOSFET) has been successfully developed that exhibits outstanding low loss. This unique feature of the FITMOS is realised by fabricating deep trenches in the n-type drift layer, by forming p-type floating islands below the individual trenches using self-aligned ion implantation, and by fabricating trench gates with a thick oxide layer on the bottom. Then, the trade-off between the drain-to-source breakdown voltage and on-resistance has been further optimised by changing the shape of the floating islands from spherical to ellipsoidal. By improving the device structure, a breakdown voltage of 91 V and specific on-resistance of 41.5 mΩ mm2 have been obtained in a 4.5×4.5 mm square device with ellipsoidal floating islands. The relationship between the device structure and the reverse recovery characteristics is also investigated.