Transmission Line Pulse System Research Articles

4H-SiC-Based ESD Protection Design With Optimization of Segmented LIGBT for High-Voltage Applications

4H-SiC is a wide-bandgap material that exhibits excellent high-temperature conductivity and high operating voltage. These characteristics can provide high electrostatic discharge (ESD) robustness in high voltage applications. However, a considerably wide range of snapback phenomena is triggered for 4H-SiC-based ESD protection devices owing to a high critical electric field. In this study, an ESD protection device based on a lateral insulated-gate bipolar transistor (LIGBT) with a new structure that creates an internal silicon-controlled rectifier (SCR) path is proposed. The proposed ESD protection device minimizes the effective base region of the NPN parasitic bipolar transistor to the gate length based on the internal SCR operation of the LIGBT. It also adjusts the emitter injection efficiency of the PNP parasitic bipolar transistor by introducing a segment topology and inserting an additional implant area. Consequently, the proposed ESD protection device significantly improves the wide range of snapback phenomena occurring in the 4H-SiC materials. A conventional SCR, the LIGBT, and the proposed protection device were fabricated using the 4H-SiC process under the same condition, and their electrical characteristics were comparatively analyzed using a transmission-line pulse system. Moreover, its high-temperature reliability was evaluated at 300–500 K to examine the compatibility with 4H-SiC devices and circuits that require a relatively high-temperature operation.

Design of a Dual-directional Diode-triggered SCR for Low Voltage ESD Protection

A novel dual-directional diode-triggered silicon controlled rectifier (DDTSCR) for low voltage electrostatic discharge (ESD) protection was designed and realized in a 0.18-µm CMOS process. Compared to the single-directional diode-triggered SCR (SDTSCR), the DDTSCR has dual-directional ESD protection performance due to the symmetric structure, and its ESD protection efficiency per unit area is about 2 times larger than that of SDTSCR under opposite ESD stresses, while remaining the similar trigger voltage of 1.68 V and the figure of merit. The human body model robustness of the DDTSCR measured by the transmission line pulse system is up to 8000 V with an area of 1400 µm2, suitable for low voltage ESD protection requirements.

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.

Analysis of Stacked AHHVSCR-Based ESD Protection Circuit with High Robustness

This paper proposes an advanced high holding voltage silicon controlled rectifier (AHHVSCR) with a new structure with an insertion of PMOS (P-type metal-oxide-semiconductor). To verify the characteristics of the proposed ESD protection circuit and analyze its operating characteristics, a comparative analysis of electrical characteristics with HHVSCR (High Holding Voltage SCR), was conducted by using TCAD simulation. HBM(Human Body Model) maximum temperature test results confirmed that the proposed ESD protection circuit has a maximum temperature value of 355K, which is about 20K lower temperature characteristic than that of HHVSCR (373K), indicating more improved robustness. In addition, the proposed ESD protection circuit was designed by applying N-STACK technology, and its applicability by voltage was verified through simulations. The proposed ESD protection circuit was designed and fabricated using 0.18um BCD process, and the validity of its electrical characteristics was confirmed using TLP (Transmission Line Pulse) system. The proposed ESD protection circuit has improved latch-up immunity with holding voltage of 18.42V, which is 7.7V higher than HHVSCR in a single structure, and it can be applied by voltage with increased holding voltage characteristics of 2-STACK 45.81V and 3-STACK 76.51V according to the application of N-STACK technology.

System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chips

This paper proposed a co-packaged methodology using transient voltage suppressor (TVS) chips and a controller area network (CAN) bus transceiver to ensure IEC 61000-4-2 system-level ESD protection. The design methodology is verified in a high-voltage silicon-on-insulator process for CAN transceiver chip and an 0.8- ${\mu }\text{m}$ bipolar process for TVS chips. The ${I}$ – ${V}$ curves of the TVS and CAN transceiver chip are evaluated by the transmission line pulsing system with the pulse width of 100 ns. The breakdown voltage of the bi-directional TVS chips and CAN transceiver chip are higher than ±80 V compared with the ±70 V fault voltage tolerance requirement. The clamping voltage of the TVS device is lower than ±130 V to discharge ESD current before the CAN transceiver chip breakdown for effective ESD protection. The design target of parasitic inductance by bonding wires is calculated to meet the clamping voltage requirement. The CAN bus transceiver IC with TVS chips co-packaged has been evaluated to pass the IEC61000-4-2 contact ±15-kV stress without any hardware damages and latch-up issues.

Robust lateral double‐diffused MOS with interleaved bulk and source for high‐voltage electrostatic discharge protection

A device with bulk and source interleaved dotting is fabricated in a 0.5-µm 24 V CDMOS process, and the root cause of why it improves the multi-finger high-voltage lateral double-diffused MOS (LDMOS)’s electrostatic discharge (ESD) robustness is detected by Atlas three-dimensional device simulation and transmission line pulse system. Such device structure obtains strong ESD robustness by enlarging the intrinsic base resistance without increasing device area and sacrificing any ESD performance of nLDMOS. The measurement results demonstrated that, compared with traditional gate-grounded nLDMOS (GG-nLDMOS) with a total length of 400 μm, the proposed device can effectively raise the secondary breakdown current (I t2) from 2.43 A up to 5.55 A, and enhance the ESD current discharge efficiency from 0.29 to 0.70 mA/μm2.

The Analysis of SCR-Based ESD Protection Circuit with P-Drift and N+ Floating Region

In this paper, a novel SCR (Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. The proposed protection circuit has high holding voltage due to floating n+ region which reduces current gain of parasitic bipolar transistor. This characteristic makes it ensure latch-up immunity. The electrical characteristics of the proposed ESD protection circuit have been simulated by using Synopsys TCAD simulation tool. According to the simulation results, the proposed protection circuit has high holding voltage of about 4.61V to 8.75V as design variation. Also, it is verified by using TLP (Transmission Line Pulse) system. As a result of measurement, it has holding voltage of 15.7V to 19.35V as design variation and high robustness above HBM 6kV, MM 600V.

Analysis of the role of the parasitic BJT of Super-Junction power MOSFET under TLP stress

The Super-Junction power Metal-Oxide-Semiconductor Field-Effect-Transistor (SJ-MOSFET) is one of the main switches in solar, lighting, consumer, server, and telecom applications. Among other market requirements a long lifetime is crucial, thus device robustness and reliability are decisive in quality assessment. Several failures are attributed to the action of the parasitic Bipolar Junction Transistor (BJT) inherent to the physical structure of the SJ-MOSFET. Our purpose is to gain insight into the role of the parasitic BJT under fast voltage pulse condition and to determine if the Transmission Line Pulse (TLP) can be used as a new method for predicting the Single Event Burnout (SEB) sensitivity of SJ-MOSFETs. SEB is caused by extreme localized triggering of the parasitic BJT while the whole device is in the off-state. However, TLP is uniform across a device and drives it into the avalanche multiplication regime. We demonstrate by direct comparison to equivalent SJ-Diodes that the parasitic BJT stabilizes the SJ-MOSFET when subjected to high voltage pulses generated by a TLP system. We conclude that the fast voltage method is not suited for emulating cosmic ray induced failure, but shows immense potential in analyzing device failure in other regimes.

Enhancement of the Electrical Safe Operating Area of Integrated DMOS Transistors With Respect to High-Energy Short Duration Pulses

The influence of the source/body layout on the electrical safe operating area (SOA) of both vertical and lateral double-diffused metal-oxide-semiconductor transistors is experimentally investigated using a transmission line pulse system. Tradeoff between RDSon ·Area and SOA is discussed. Stripe geometries with and without (i.e., conventional design) body contact extension and cell designs with circular and oval geometries are considered. It is shown that a circular design of the source/body cell is superior with respect to SOA, compared with the conventional stripe design. The oval design is used to improve RDSon ·Area without compromising SOA performance, compared with the circular design.

On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs

An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100ns TLP system. From the HBM/CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1kV, MM 100V and CDM 500V.

Investigation on Robustness of CMOS Devices Against Cable Discharge Event (CDE) Under Different Layout Parameters in a Deep-Submicrometer CMOS Technology

Cable discharge events (CDEs) have been found to be the major root cause of inducing hardware damage on Ethernet ICs of communication interfaces in real applications. Still, there is no device-level evaluation method to investigate the robustness of complementary metal-oxide-semiconductor (CMOS) devices against a CDE for a layout optimization in silicon chips. The transmission-line pulsing (TLP) system was the most important method used to observe the electrical characteristics of semiconductor devices under human-body model (HBM) electrostatic discharge (ESD) stress. To understand the physical characteristics and CDE robustness of on-chip protection devices, the long-pulse transmission-line pulsing (LP-TLP) system is proposed in this paper and used to simulate the influence of CDE on Ethernet-integrated circuits. The secondary breakdown characteristics of the CDE protection devices under different layout styles and parameters can be measured and analyzed by the proposed LP-TLP with pulsewidths of 500 or 1000 ns. Furthermore, measured results using the LP-TLP system are compared with results measured by the traditional 100-ns TLP system. The experimental results with silicon devices in 0.18-mu m CMOS process have shown that the CDE robustness of n-channel metal-oxide-semiconductor (NMOS) and p-channel metal-oxide-semiconductor (PMOS) devices in deep-submicrometer CMOS technology is much lower than their HBM ESD robustness. By using the proposed LP-TLP system, one set of design rules for I/O devices to sustain high CDE robustness in a given CMOS process can be evaluated and built up for chip layout.

Investigation on the Validity of Holding Voltage in High-Voltage Devices Measured by Transmission-Line-Pulsing (TLP)

Latch-up is one of the most critical issues in high-voltage (HV) ICs due to the high power-supply voltages. Because the breakdown junction of an HV device is easily damaged by the huge power generated from a DC curve tracer, the device immunity against latch-up is often referred to the transmission-line-pulsing (TLP)-measured holding voltage. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25- 18-V bipolar CMOS DMOS process to evaluate the validity of latch-up susceptibility by referring to the holding voltage measured by 100- and 1000-ns TLP systems and curve tracer. Long-pulse TLP measurement reveals the self-heating effect and self-heating speed of the n-channel LDMOS. The self-heating effect results in the TLP system to overestimate the holding voltage of HV n-channel LDMOS. Transient latch-up test is further used to investigate the susceptibility of HV devices to latch-up issue in field applications. As a result, to judge the latch-up susceptibility of HV devices by holding voltage measured from TLP is insufficient.

TLP calibration, correlation, standards, and new techniques

This paper describes a constant impedance transmission line pulse system with new measurement capabilities and improved accuracy. The paper enforces a broader look at transmission line pulse (TLP) data, beyond the I-V curves. Accurate TLP measurements and actual TLP/HBM device data are used to demonstrate dV/dt effects and HBM/TLP correlation and miscorrelation. Finally, a calibration method and standard TLP test method are presented for adaptation by the industry. This is necessary to provide correlation and repeatability of experimental data.